PIC18F66K80 family: Does CCP in Compare mode *latch* its output pin?
I've always presumed that when a CCP module is configured in Compare mode and driving its output pin, once the CCP and Timer match the pin state is switched and stays there. However, I'm seeing some behavior - which I haven't absolutely confirmed yet - that seems like maybe it does not.
In section 19.0 of the PIC18F66K80 spec sheet, page 247, CCP Module Mode 0b1001 (9) is described as follows: "Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set)". The question is, what happens if the underlying Timer continues to count past the matching value? The text in section 19.3 "Compare Mode" is vague.
Looking at the block diagram for Compare mode in Figure 19-2 (page 254) doesn't really answer the question either. From the "comparator" block there is a signal named "Compare Match". It's not clear if that signal, or the "Output Logic" it drives, latches like a one-shot once the match occurs (and thus holds its output pin low indefinitely) or if it dynamically indicates a match (which means its output pin could pulse low for the length of one Timer count and then go back high again when a mismatch recurs). Note that the "Output Logic" has control of both Set and Reset for the pin; it obviously needs those so it can operate the pin in either polarity, and I want to believe it only triggers the pin in one direction, but there's nothing definitive about that.
The Compare modes can set the associated interrupt flags, but again the spec sheet isn't clear if that is also how the pins are handled. With respect to the interrupt flags the spec sheet is very clear: "CCPxIF bit is set" (page 247) and "Set CCPxIF" (Figure 19-2). But the pins don't use terms like "set" and "clear", they say "on compare match, force...". Which might mean "on compare MISmatch, force the other way".
I'm going to set up a test to see what happens, but if someone already knows the answer I'd sure appreciate saving the time. Thanks!