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Hot!dsPIC33CK256MP506 hysteretic mode configuration for PWM and Comparator

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Sparkie
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2019/04/29 13:41:16 (permalink)
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dsPIC33CK256MP506 hysteretic mode configuration for PWM and Comparator

I am using the dsPIC33CK506 in a new power supply design. We are going to run the output half-bridge in hysteretic mode. I previously set this up successfully on a dsPIC33EPxxxGS family part and had it working.
 
I have setup a simple test circuit on a board to get this working. The output of PWM5H is charges an RC filter and this signal is fed to the current sense ADC on AN1.
Comparator 1 is setup in hysteretic mode with AN1 as the positive input (CMP1D)
 
if the PWM is setup to produce a standard complementary output, the comparator output and DAC output voltage seem to be correct for hysteretic mode control. The DAC output voltage transitions to the high dac value on the rising edge of PWM5H and then transitions down to the lower dac value on the falling edge of PWM5H. Transition mode is set so the transition is very fast.
 
The comparator output also appears to be correct as it goes high when the current signal goes above the high dac value (goes low again on the trailing edge of PWM5H when the dac output changes to the low output setting) and then goes high again when the current signal goes below the lower dac output voltage. (See Photo)
 
The problem is that I can not figure out what the correct settings are to get the PWM output to properly toggle on and off based on the comparator output. Unfortunatly the example for hysteretic mode in the analog comparator module family datasheet is somewhat does not seem to work. It may be incomplete as there are several PWM registers that it does not configure.
 
It sets the duty cycle to zero. It is not clear to me how the PWM is configured so the comparator can control the PWM pins. In hysteretic mode I do not see the current-limit status active for example.
 
The second photo is a screen-shot of my GUI that I have configured to be able to quickly change settings for this. These are the settings that were operational for the first photo.
Since I can try different things very quickly, any and all thoughts and ideas are welcome. If anyone has actually gotten this to work and can explain how the PWM is controlled by the comparator, all the better.
 
This is an amazing chip btw. Considering the ground-up redesign of many of the peripherals, the errata on it shows how much effort must have been put into testing and simulating.
 
 
 
 
 
 

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4 Replies Related Threads

    spdmtl
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    Re: dsPIC33CK256MP506 hysteretic mode configuration for PWM and Comparator 2019/04/29 14:33:15 (permalink)
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    Hi Sparkie,
     
    On the CK device, each PWM has four PWM Control Input (PCI) blocks for output pin control, among other things.  The comparator(s) can be selected as the input to the PCIs. Judging from gui pic you already program it.
    Any of the 3 PCIs other than 'sync' can be used to gate output. 
     
     
    You have 0001 0010 0111 1011 for pg5clpcil
    so comp1 is pps input, inverted and sync'd to EOC. AQSS is 'LEB' and TERM is TRIGA. latched mode.
     
    If I understand correctly, you want to stop/gate (0% DC) when comp is high and resume some pre-set DC otherwise?
    Should be as simple as selecting the PSS. 000 000 0001 1011. if so, get that working and then add LEB (which usually needs to be inverted via AQPS and use auto term)
    good luck
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    Sparkie
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    Re: dsPIC33CK256MP506 hysteretic mode configuration for PWM and Comparator 2019/04/29 15:10:13 (permalink)
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    Thanks for the reply,
     
    I think you skipped a bit reading the gui pic as the TERM event is already set to Auto Terminate, not TRIGA
    PPS is also set to 11011 already, which is the comparator 1 output.
     
    The goal here is to have both the duty cycle and the PWM frequency totally controlled by the current signal bouncing between the two DAC output settings. So far, all I can seem to get it to do is what is in the picture, or, nothing at all. 
     
    Bob
     
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    VDimitrov
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    Re: dsPIC33CK256MP506 hysteretic mode configuration for PWM and Comparator 2019/06/10 12:28:49 (permalink)
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    Hi Bob,
     
    I have figured it out.
     
    In my setup i have an external comparator connected to PCI8. The inverting input is connected to DACOUT1, and the noninverting to the current feedback signal (the same composition as the one integrated in the chip)
     
    The changes I made to the example in are:
    PG1CLPCILbits.TSYNCDIS=1;//Termination of latched PCI occurs immediately 
    PG1CLPCILbits.AQPS=1;//invert
     
    PG1CLPCIHbits.TQSS=2;//LEB
    PG1CLPCIHbits.TQPS=1;//invert
     
    PG1IOCONHbits.PMOD=1; // Set the outputs in independent mode
    PG1LEBHbits.PHF=1;//Add LEB to both fronts
    PG1LEBHbits.PHR=1;
    The other bits are the same, as the example code.
     
    Also, in the configuration of the DAC i have changed the SSTIME and TMODTIME.
    This is a little bit tricky and i have not made extensive tests yet to determine the best values, but with: 
     
    DACCTRL2Hbits.SSTIME = 0x350; 
    DACCTRL2Lbits.TMODTIME =0;
    it works.
     
    Also, I am using  FPLL0 as clock source, so DACCTRL1Lbits.CLKSEL = 3;
     
    Hope this helps. 
     
    Vlado
     
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    spdmtl
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    Re: dsPIC33CK256MP506 hysteretic mode configuration for PWM and Comparator 2019/10/10 09:03:13 (permalink)
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    VDimitrov
    Hi Bob,
     
    I have figured it out.
     
    In my setup i have an external comparator connected to PCI8. The inverting input is connected to DACOUT1, and the noninverting to the current feedback signal (the same composition as the one integrated in the chip)
     
    The changes I made to the example in are:
    PG1CLPCILbits.TSYNCDIS=1;//Termination of latched PCI occurs immediately 
    PG1CLPCILbits.AQPS=1;//invert
     
    PG1CLPCIHbits.TQSS=2;//LEB
    PG1CLPCIHbits.TQPS=1;//invert
     
    PG1IOCONHbits.PMOD=1; // Set the outputs in independent mode
    PG1LEBHbits.PHF=1;//Add LEB to both fronts
    PG1LEBHbits.PHR=1;
    The other bits are the same, as the example code.
     
    Also, in the configuration of the DAC i have changed the SSTIME and TMODTIME.
    This is a little bit tricky and i have not made extensive tests yet to determine the best values, but with: 
     
    DACCTRL2Hbits.SSTIME = 0x350; 
    DACCTRL2Lbits.TMODTIME =0;
    it works.
     
    Also, I am using  FPLL0 as clock source, so DACCTRL1Lbits.CLKSEL = 3;
     
    Hope this helps. 
     
    Vlado
     


    The latest revisions of the CK datasheets now include the PPS signals (pwm_req_on/off[n]) that interface the PWM to the DAC/CMP.  The FRM has updated example code for hysteretic mode.
     
    Also SSTIME and TMODTIME values are directly based on input clock, which should be 500 MHz.  They just hold off the DAC from going into the next mode.  The default values are correct for 500 Mhz operation and should be left as is.
     
     
    #5
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