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acharnley
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2019/04/23 08:34:55 (permalink)
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PIC16/18 - Fudging Two Extra Gates

Can anyone think of a way to resolve the logic (in hardware) on the PIC16/18? There is a future PIC18 coming out with 8 gates but until then all I can think off is two PIC's.

Cheers, Andrew

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#1

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    Howard Long
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    Re: PIC16/18 - Fudging Two Extra Gates 2019/04/24 04:24:07 (permalink)
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    Any PIC with four CLCs configured as AND-OR could achieve this. Remember that you can make the OR-AND from AND-OR by inverting all inputs and the output.
    #2
    acharnley
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    Re: PIC16/18 - Fudging Two Extra Gates 2019/04/24 05:10:26 (permalink)
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    I'm not seeing it, there are 6 outputs and the two (right side) are not an inversion of any other 4?

    I'm aware that each CLC has 4 AND gates feeding into two OR gates but there's ultimately only one input (or an inversion).
    #3
    NorthGuy
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    Re: PIC16/18 - Fudging Two Extra Gates 2019/04/24 05:24:16 (permalink)
    +1 (1)
    If you use CLCs, one CLC can produce only one output. So, to produce 6 outputs, you need 6 CLCs.
     
    You may be able to achieve your goal by using HLT timers, which can be gated by posCycle/negCycle. If you then use the timers to drive PWM, it'll effectively gate the PWM. But even if you do, you still won't have enough of them.
     
    External logic ICs, or even a small CPLD may do this.
    #4
    acharnley
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    Re: PIC16/18 - Fudging Two Extra Gates 2019/04/24 05:36:16 (permalink)
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    I'm short on HLT's anyhow, those are my operational gold dust.

    Microchip have a new PIC18 coming out with... 8 CLC's, but when it'll be available I don't know.
    #5
    Howard Long
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    Re: PIC16/18 - Fudging Two Extra Gates 2019/04/24 06:16:53 (permalink)
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    Ah, sorry my mistake. Let me see what I can do with a pair of DSMs as well.
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    Howard Long
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    Re: PIC16/18 - Fudging Two Extra Gates 2019/04/24 06:20:15 (permalink)
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    Is there any correlation between poscycle and negcycle? I.e., is one simply the inverted version of the other?
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    Howard Long
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    Re: PIC16/18 - Fudging Two Extra Gates 2019/04/24 07:37:28 (permalink)
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    Assuming there is no correlation between poscycle and negcycle, you can fabricate the left hand side with four CLCs and the right hand side with three DSMs.
     
    To make a two input AND gate with a DSM:
     
    CHSYNC=0
    CLSYNC=0
    MOD= Input A
    CH=0 (some DSM muxes might allow this directly, otherwise assign to a spare or virtual pin and pull low)
    CL= Input B
    CHPOL=0
    CLPOL=0
    OPOL=0
     
    To make a two input OR gate with a DSM:
     
    CHSYNC=0
    CLSYNC=0
    MOD= input A
    CH= Input B
    CL=0 (some DSM muxes might allow this directly, otherwise assign to a spare or virtual pin and pull low)
    CHPOL=1
    CLPOL=0
    OPOL=0
     
    The following devices that have CLC >= 4 and DSM >= 3.
     
    PIC16F1773
    PIC16F1776
    PIC16F1777
    PIC16F1778
    PIC16F1779
     
    In addition, if your signals are generated by the PIC, there may be many other options that are integrated with the PWM peripheral, or other bolt-ons such as CWG/COG. In this case it is better to understand at a higher level what you're trying to achieve to offer a system defined solution rather than a component based one. PIC PIC16F177x series for example already have quite comprehensive PWM steering mechanisms, as well as several COGs to provide deadtime generation facilitating push-pull and bridge scenarios.
     
    post edited by Howard Long - 2019/04/24 14:26:25
    #8
    Howard Long
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    Re: PIC16/18 - Fudging Two Extra Gates 2019/04/24 14:29:14 (permalink)
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    Some code for a PIC16LF1776 demonstrating using the DSMs for AND and OR gates.
     


    // PIC16LF1776 Configuration Bit Settings
    // 'C' source line config statements
    // CONFIG1
    #pragma config FOSC = INTOSC // Oscillator Selection Bits (INTOSC oscillator: I/O function on CLKIN pin)
    #pragma config WDTE = OFF // Watchdog Timer Enable (WDT disabled)
    #pragma config PWRTE = OFF // Power-up Timer Enable (PWRT disabled)
    #pragma config MCLRE = ON // MCLR Pin Function Select (MCLR/VPP pin function is MCLR)
    #pragma config CP = OFF // Flash Program Memory Code Protection (Program memory code protection is disabled)
    #pragma config BOREN = OFF // Brown-out Reset Enable (Brown-out Reset disabled)
    #pragma config CLKOUTEN = ON // Clock Out Enable (CLKOUT function is enabled on the CLKOUT pin)
    #pragma config IESO = OFF // Internal/External Switchover Mode (Internal/External Switchover Mode is disabled)
    #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable (Fail-Safe Clock Monitor is disabled)
    // CONFIG2
    #pragma config WRT = OFF // Flash Memory Self-Write Protection (Write protection off)
    #pragma config PPS1WAY = OFF // Peripheral Pin Select one-way control (The PPSLOCK bit can be set and cleared repeatedly by software)
    #pragma config ZCD = OFF // Zero-cross detect disable (Zero-cross detect circuit is disabled at POR)
    #pragma config PLLEN = OFF // Phase Lock Loop enable (4x PLL is enabled when software sets the SPLLEN bit)
    #pragma config STVREN = ON // Stack Overflow/Underflow Reset Enable (Stack Overflow or Underflow will cause a Reset)
    #pragma config BORV = LO // Brown-out Reset Voltage Selection (Brown-out Reset Voltage (Vbor), low trip point selected.)
    #pragma config LPBOR = OFF // Low-Power Brown Out Reset (Low-Power BOR is disabled)
    #pragma config LVP = ON // Low-Voltage Programming Enable (Low-voltage programming enabled)
    // #pragma config statements should precede project file includes.
    // Use project enums instead of #define for ON and OFF.
    #include <xc.h>
    #include <stdint.h>
    #define _XTAL_FREQ 500000
    int main(void)
    {
    uint8_t u8=0;
    TRISA=0;
    TRISC=0;
    ANSELA=0;
    ANSELC=0;

    // DSM 2-input gate example setup
    // RA0 is a dummy pin always low to feed the unused gate input of the DSMs
    // RC0 is input A, generated by main superloop
    // RC1 is input B, generated by main superloop
    // RC2 is MD1_out (A AND B)
    // RC3 is MD2_out (A OR B)
    LATAbits.LATA0=0; // Zero pin for unused input to DSM gate
    // DSM1 setup, AND gate
    MD1MODPPSbits.MD1MODPPS=0b010000; // RC0 input A to MOD
    MD1CHPPSbits.MD1CHPPS=0b000000; // RA0, should always be zero
    MD1CLPPSbits.MD1CLPPS=0b010001; // RC1 input B to CL
    RC2PPSbits.RC2PPS=0b101110; // 0b101110 => MD1_out on RC2

    MD1CON1bits.CHSYNC=0;
    MD1CON1bits.CLSYNC=0;
    MD1SRCbits.MS=0b00000; // 0b00000 => MOD input is PPS pin
    MD1CARHbits.CH=0b00000; // 0b00000 => CH input is PPS pin
    MD1CARLbits.CL=0b00000; // 0b00000 => CL input is PPS pin
    MD1CON1bits.CHPOL=0;
    MD1CON1bits.CLPOL=0;
    MD1CON0bits.OPOL=0;
    MD1CON0bits.EN=1;

    // DSM2 setup, OR gate
    MD2MODPPSbits.MD2MODPPS=0b010000; // RC0 input A to MOD
    MD2CHPPSbits.MD2CHPPS=0b010001; // RC1 input B to CH
    MD2CLPPSbits.MD2CLPPS=0b000000; // RA0, should always be zero
    RC3PPSbits.RC3PPS=0b101111; // 0b101111 => MD2_out on RC3

    MD2CON1bits.CHSYNC=0;
    MD2CON1bits.CLSYNC=0;
    MD2SRCbits.MS=0b00000; // 0b00000 => MOD input is PPS pin
    MD2CARHbits.CH=0b00000; // 0b00000 => CH input is PPS pin
    MD2CARLbits.CL=0b00000; // 0b00000 => CL input is PPS pin
    MD2CON1bits.CHPOL=1;
    MD2CON1bits.CLPOL=0;
    MD2CON0bits.OPOL=0;
    MD2CON0bits.EN=1;

    while (1)
    {
    LATC=u8++ & 0x3; // Generate inputs A and B on RC0 and RC1
    }
    return 0;
    }

     
     

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    acharnley
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    Re: PIC16/18 - Fudging Two Extra Gates 2019/04/24 15:33:44 (permalink)
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    Sorry for my delay. "poscycle" is a AC crossover point which I'm determining using the comparator and a home brew 0.1v source using a diode and three resistors (the DAC is used by the other comparator). The voltage range is outside the 5x of the ZCD hence homebrew.
     
    Technically poscycle and negcycle can both be zero but that's handled by pwmA and pwmB, which is generated by a CWG. The second comparator is set to trip the CWG (so no output on either channel). Technically I'd have rather tripped it on several conditions (comparator + two pin interrupts + timer) but that would require another CLC, so the main CPU still has interrupts for the extras and applies logic manually).
     
    I've played with those PIC16 series of chips and I didn't get on with them, I found they were two focused on switch current-mode and skimped in other areas (the ADC is uber basic and fluctuated compared to my go to chip the the PIC18(L)F24/25K42).

    Very interesting using the DSM in that way. I'll try it out tomorrow morning.
    #10
    Howard Long
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    Re: PIC16/18 - Fudging Two Extra Gates 2019/04/25 01:11:03 (permalink)
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    Unfortunately the K42 series only have a single DSM from my recollection. You can also use DSM modules to make other functions such as a 2:1 mux, an XOR gate, an inverter, and I am sure there are others.
     
    Regarding the ZCD, as you probably know it's current controlled, not voltage controlled, so you use resistors to set the voltage range. I'm intrigued now as to why this doesn't work in your application!
     
    #11
    NorthGuy
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    Re: PIC16/18 - Fudging Two Extra Gates 2019/04/25 05:40:00 (permalink)
    +1 (1)
    If posCycle and negCycle cannot be '1' at the same time and you already turn off PWM when they're both '0', then you can simplify things:
     
    - the AND gates on the left side of the IC can be removed
    - the right side can be derived from the left: A9 <= A22 and A24; A11 <= A4 and A26;
    #12
    Howard Long
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    Re: PIC16/18 - Fudging Two Extra Gates 2019/04/25 06:49:01 (permalink)
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    NorthGuy
    If posCycle and negCycle cannot be '1' at the same time and you already turn off PWM when they're both '0', then you can simplify things:
     
    - the AND gates on the left side of the IC can be removed
    - the right side can be derived from the left: A9 <= A22 and A24; A11 <= A4 and A26;




    I agree, understanding valid states can be very key to minimising combinational logic, this is what I was alluding to when I suggested that knowing what was trying to be achieved as a system or higher level can lead to significantly differing solutions to a strictly component based approach.
     
    I am wondering if there are also similar invalid states regarding pwmA and pwmB.
    post edited by Howard Long - 2019/04/25 06:51:49
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    acharnley
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    Re: PIC16/18 - Fudging Two Extra Gates 2019/04/25 08:38:44 (permalink)
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    Re: ZCD

    I'm interested in 0v (or close too) to 100V AC, while the ZCD only has a bandwidth of 5x. In other words using an appropriate resistor to reach the maximum permitted current at 100V means it'll only zero detect at 20V and above. That and the fact crossover is at 0.75V (I have varying AC frequency so I can't phase compensate) make it rather unhelpful. :)

    Re: Gates

    That doesn't seem right Northguy. A little more explanation first, there is a PWM and it's CWG inversion (pwmA and pwmB) and based on the AC polarity these switch-mode to the inductor. When posCycle = true, M3 is pulsing, M4 is on, M5 is on and M6 is the inversion. Typical buck-sync design.
     
    If you're wondering why the upper and lower fets are not driven together it allows the buck to work in DCM mode.

    The right side basically only completes the circuit when pwmA or pwmB are active for the AC polarity of interest, this prevents the AC pulling power from the load when pwm is off.

    What I can see working is to have two pwm/cwg combinations, one for each cycle. That gets rid of the AND gates on the left, perhaps that's what you were referring to Northguy?
    post edited by acharnley - 2019/04/25 08:43:46
    #14
    acharnley
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    Re: PIC16/18 - Fudging Two Extra Gates 2019/04/25 09:09:37 (permalink)
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    With two PWM/CWG pairs.
     
    If I could guarantee DCM (LTspice says it will at the extremes) won't happen then I could drive the left FET's together, and then it's just a case of inverting the polarity of the CWG based on (posCycle). This would turn the right gates into AND's.

    What I need is Microchip to release that new PIC18 :)

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    NorthGuy
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    Re: PIC16/18 - Fudging Two Extra Gates 2019/04/25 13:52:39 (permalink)
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    acharnley
    What I can see working is to have two pwm/cwg combinations, one for each cycle. That gets rid of the AND gates on the left, perhaps that's what you were referring to Northguy?



    I think I misunderstood what you're doing. What I meant is this:
     
    If you look at the effect of the logic circuit which produces signal at p0, it is (the first digit is posCycle, the second is negCycle):
     
    when "11" => p0 <= '1';
    when "10" => p0 <= pwmA;
    when "01" => p0 <= '1';
    when "00" => p0 <= '0';

     
    If your pwmA is already at zero when both posCycle and negCycle are '0', then it is the same as:
     
    when "11" => p0 <= '1';
    when "10" => p0 <= pwmA;
    when "01" => p0 <= '1';
    when "00" => p0 <= pwmA;

     
    In this case, the result doesn't depend on posCycle at thus the AND gate can be removed.
    #16
    acharnley
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    Re: PIC16/18 - Fudging Two Extra Gates 2019/04/25 15:05:55 (permalink)
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    Yup that's correct and aligns with the one a post up where the AND's are removed. They're actually still there but hidden as it's the way to mimic the PIC's logic. I don't need two PWM/CWG's but the right hand gates are still feeding in both values of the CWG (so ~99% duty after deadtime).
     
    Looks like 6 gates is still the minimum. At worst I can use interrupts to define the LAT value to the right gates.
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    NorthGuy
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    Re: PIC16/18 - Fudging Two Extra Gates 2019/04/25 15:34:57 (permalink)
    +1 (1)
    acharnley
    Looks like 6 gates is still the minimum. At worst I can use interrupts to define the LAT value to the right gates.



    If you have time to do so from CPU, the easiest way is to enable/disable/re-route everything manually as needed at the zero crossing.
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    Howard Long
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    Re: PIC16/18 - Fudging Two Extra Gates 2019/04/26 01:01:24 (permalink)
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    acharnley
    Re: ZCD

    I'm interested in 0v (or close too) to 100V AC, while the ZCD only has a bandwidth of 5x. In other words using an appropriate resistor to reach the maximum permitted current at 100V means it'll only zero detect at 20V and above. That and the fact crossover is at 0.75V (I have varying AC frequency so I can't phase compensate) make it rather unhelpful. :)

     
    OK, understood. The ZCD isn't really designed for variable voltage.
     
    (If you're looking for unexpected applications, I have used the ZCD very successfully as a key part of an RFID reader demodulator.)
     
    #19
    NorthGuy
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    Re: PIC16/18 - Fudging Two Extra Gates 2019/04/26 07:28:25 (permalink)
    +1 (1)
    BTW: Looks like PIC18F26Q10 and PIC18F27Q10 are already available and have 8 CLCs.
    #20
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