About PPS mapping for I2C pins, it is actually pointed out in the datasheet DS40001897B
Page 6, Table 3: 8-Pin allocation table, pay attention to the Notes!
RA1 pin 6, column MSSP: SCL1(1,4)
RA2 pin 5, column MSSP: SDA1(1,4)
further down in the table,
OUT(2), column MSSP: SCL1(3,4)
OUT(2), column MSSP: SDA1(3,4)
Note 1: This is a PPS remappable input signal.
The input function may be moved from the default location shown to one of several other PORTx pins.
2: All digital output signals shown in this row are PPS re-mappable.
These signals may be mapped to output onto one of several PORTx pin options.
3: This is a bidirectional signal. For normal module operation,
the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins are configured for I2C logic levels.
PPS assignments to the other pins will operate,
but input logic levels will be standard TTL/ST as selected by the INLVL register,
instead of the I2C specific or SMBUS input buffer thresholds.
Page 15: TABLE 1-2:
Signal SCL1 (1,2)
Signal SDA1 (1,2) Pay attention to the Notes!
Page 17: TABLE 1-2 PIC16(L)F15313 PINOUT DESCRIPTION (CONTINUED)
Pay attention to the Notes!
Page 189: 15.3 Bidirectional Pins
Read the big Note block.
Page 361: FIGURE 32-2: MSSP BLOCK DIAGRAM (I2C MASTER MODE)
Note 1: SDA pin selections must be the same for input and output.
1: SCL pin selections must be the same for input and output.
Page 362: FIGURE 32-3: MSSP BLOCK DIAGRAM (I2C SLAVE MODE)
Read the Notes.
Page 371: 32.4.3 SDA AND SCL PINS
Read the paragraph and the big Note block.
post edited by Mysil - 2019/04/22 06:19:40