• AVR Freaks

Hot!Is there a way to synchronize K42's DMA ?

Author
Aeroman66
New Member
  • Total Posts : 7
  • Reward points : 0
  • Joined: 2019/03/07 09:56:18
  • Location: 0
  • Status: offline
2019/04/10 03:49:43 (permalink)
0

Is there a way to synchronize K42's DMA ?

Hi,
 
        I am trying to use a timer to control a DMA transfer in order to move a byte from RAM to a GPIO port every timer tick, but it seems to be that this works only for the first byte, and I have to clear the timer's interrupt flag in order to allow the next tick to trigger the next byte transfer.
        Are there any ways to do that? It works really nice with SPI and UART, as they will clear the buffer full flag on read or write, but for the timer, the only way I found to do it is to clear the flag manually
 
       Thanks!
#1

4 Replies Related Threads

    AMAK
    Super Member
    • Total Posts : 52
    • Reward points : 0
    • Joined: 2014/08/05 10:45:57
    • Location: 0
    • Status: offline
    Re: Is there a way to synchronize K42's DMA ? 2019/04/10 07:49:18 (permalink)
    0
    Can you share some code? It would be easier to look at how you have setup the DMA and timer
    #2
    Aeroman66
    New Member
    • Total Posts : 7
    • Reward points : 0
    • Joined: 2019/03/07 09:56:18
    • Location: 0
    • Status: offline
    Re: Is there a way to synchronize K42's DMA ? 2019/04/10 09:28:30 (permalink)
    0
    The code now is really big, and split between files, so I had to do some copy and paste of the important stuff below. Sorry for the comments in portuguese
    The idea is that I have a 129 bytes buffer in RAM pointed by R_RenderPtr *256, and they should be sent through PORTC on the frequency set by TMR0, on a window set by CCP3. CLC2 is used to AND both signals.
    This signal is ok, I've measured it using a oscilloscope on the output pin set for CLC2, but the DMA is moving only the first byte of the buffer to PORTC. If I clear CLC2IF, it will send the second byte.
    I have made a test, using TMR0 as the trigger to DMA directly, and got the same result. A second test was made using IOC (as this SIRQ source is level triggered)  set on the same output pin I've measured the signal, and I got the entire buffer sent, but all bytes were transfered completely out of sync with TMR0
     
    Here is the code...
     
        
     ;configuramos os timers
     banksel T1CLK
        movlw B'00000001' ;clock em 14MHz
        movwf T1CLK
        movwf T2CLK
        movwf T4CLK
        movwf T6CLK
        clrf T0CON0 ;T0 8 bits, postscaler 0, desabilitado
        movlw B'01010001' ;clock em FOSC/4, assincrono, prescaler 2
        movwf T0CON1
        movlw 1
        movwf TMR0H
        movlw B'00000011' ;T1 leitura e escrita em 16 bits. Habilitado
        movwf T1CON
        movlw B'00100000' ;T2 e T4 prescaler de 4, então temos clock de 3.58 - color clock
        movwf T2CON
        movwf T4CON
        clrf T6CON ;T6 tem prescaler de 1 - trabalhamos com o PWM a 63kHz
        movlw SYNC_SIZE ;Carregamos o tamanho do sync em T2
        movwf T2PR
        movlw LINE_SIZE-1 ;o periodo destes timers é o comprimento de uma linha
        movwf T4PR
        movwf T6PR


     ;configuramos DMA
        banksel DMA1PR
        clrf DMA1PR ;maxima prioridade para DMA 1
        movlw 1
        movwf DMA2PR
        movlw 2
        movwf ISRPR
        movlw 3
        movwf MAINPR
        banksel PRLOCK ;garantimos acesso a memoria para a DMA
        movlw 0x55
        movwf PRLOCK
        movlw 0xAA
        movwf PRLOCK
        bsf PRLOCK,0 ;sequencia da Microchip para travar

     ;CCP3
     banksel CCP3CON
     movlw B'00001010' ;CCP3 em compare, serve para agendar as interrupçoes de video
        movwf CCP3CON
        clrf CCPR3H ;a primeira int sera para sair do vblank e ligar a borda
        movlw BORDER_POS ;em BORDER_POS clocks
        movwf CCPR3L

     
     ;configuramos o CLC
        banksel CLC1CON
        clrf CLC1CON ;desabilitamos todos
        clrf CLC2CON
        clrf CLC3CON
        clrf CLC4CON
     
     ;CLC2 comanda SELPIX, e dependendo do modo usa SPI ou timer 4. Usamos SPI por default
     ;o CCP2 controla a janela de exibição dos graficos para os modos que usam a SPI
        movlw B'00001100' ;selecionamos timer 0
        movwf CLC2SEL0
        movlw B'00010101' ;selecionamos CCP2
        movwf CLC2SEL1
        movlw B'00000010' ;as duas entradas farão AND sem inversao
        ;movlw B'00000100'
        movwf CLC2GLS0
        movlw B'00001000'
        movwf CLC2GLS1
        ;clrf CLC2GLS1
        clrf CLC2GLS2
        clrf CLC2GLS3
        movlw B'00001100' ;polaridade normal, outras celulas invertidas
        movwf CLC2POL
        movlw B'10000010' ;configuamos como and de 4 entradas, sem interrupções e ligamos
        movwf CLC2CON

     
        ;ligamos os timers, dando inicio ao video
        banksel T0CON0
        bsf T0CON0,T0EN
        bsf T2CON,T2ON
        bsf T4CON,T4ON
        bsf T1CON,TMR1ON
        bsf T6CON,T6ON
        bsf CCP1CON,EN
        bsf CCP2CON,EN
        bsf CCP3CON,EN
        bsf CCP4CON,EN



     ;configuramos a DMA1
        banksel DMA1CON0
        movlw B'01000000' ;DMA habilitada
        movwf DMA1CON0
        movlw B'00000011' ;paramos quando o destination chegar no fim e incrementamos os ponteiros de source a cada byte
        movwf DMA1CON1
        clrf DMA1SSAU
        movf R_RenderPtr,w,A ;apontamos a fonte para o buffer de render
        movwf DMA1SSAH
        clrf DMA1SSAL
        movlw HIGH LATC ;apontamos o destino para o color bus
        movwf DMA1DSAH
        movlw LOW LATC
        movwf DMA1DSAL
        movlw 129 ;o comprimento será de 129 bytes - 2 pixels por byte + 1 byte de borda
        movwf DMA1SSZL
        movlw 129
        movwf DMA1DSZL
        clrf DMA1SSZH
        clrf DMA1DSZH
        movlw 60 ;disparamos a DMA1 quando CLC2 gerar uma interrupção
        movwf DMA1SIRQ
     
     bsf DMA1CON0,EN ;armamos a DMA

    post edited by Aeroman66 - 2019/04/10 09:30:54
    #3
    NKurzman
    A Guy on the Net
    • Total Posts : 17485
    • Reward points : 0
    • Joined: 2008/01/16 19:33:48
    • Location: 0
    • Status: offline
    Re: Is there a way to synchronize K42's DMA ? 2019/04/10 10:52:42 (permalink)
    0
    Why can't you use the TMR0 Interrupt to move the Byte?
    I have not read the Data sheet,  But I I do not think DMA pacing is a common feature.
    #4
    Aeroman66
    New Member
    • Total Posts : 7
    • Reward points : 0
    • Joined: 2019/03/07 09:56:18
    • Location: 0
    • Status: offline
    Re: Is there a way to synchronize K42's DMA ? 2019/04/10 12:13:28 (permalink)
    0
    I'm doing video by software, so I need to be real fast. Setting up a interrupt would be too slow, unfortunately
     
     
    #5
    Jump to:
    © 2019 APG vNext Commercial Version 4.5