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oliverb
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2019/04/08 13:53:49 (permalink)
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PWM with a variable frequency timebase?

Looking at a K42 PIC presently, though possibly any other NCO-equipped part. I saw that timer 2 could be clocked from the NCO, but apparently this configuration is incompatible with PWM?
Is there any straightforward way to use the NCO to clock a counter to produce a variable-duty waveform?
 
Oh BTW to clarify: I'm setting TMR2 to 99, so that the PWM duty can be set in "percent".
 
Without using TMR2/CCP the only way I can see involves:
Routing the NCO1 output to Timer 1 via a CLC (no direct route?).
Creating a periodic timer using a CCP.
Setting two more CCPs to pulse output to make a set and reset pulse.
Using a CLC as a S-R latch to convert the two pulses into one waveform?
 
 
post edited by oliverb - 2019/05/20 10:31:23
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    AMAK
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    Re: PWM with a variable frequency timebase? 2019/04/08 14:53:17 (permalink)
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    Did you consider using the CWG? I think the NCO can be used as an input source to the CWG module.
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    oliverb
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    Re: PWM with a variable frequency timebase? 2019/04/09 00:51:11 (permalink)
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    I hadn't looked at CWG, but looking now I don't think it helps, it appears to be a more versatile version of the earlier "ECCP" steering function so to produce variable width output it still needs a variable width input.
     
    I think where my plan falls down is that the functions I want to use probably all need to be synchronised to the instruction clock (Fosc/4). The rules don't seem to be stated explicitly but MCC complains if I try to configure a different clock source, and it is clearly stated that the "compare" functions do need a synchronised clock.
     
    I have another plan...
     
    I'm wondering if I can use "hardware gate" instead, use FOSC/4 as the clock, but use the NCO1 signal stretched to 4 cycles as the gate for Timer 2. The stretch is to ensure the pulse lasts one instruction cycle so it won't get missed, and since NCO1 isn't in the table of reset sources I probably have to expend another CLC block to route it? The net result should be that the counter only counts when NCO1 pulses, but technically the clock source is still Fosc/4 so the requirement for PWM should still be met?
     
    The output would have more jitter compared to using NCO directly, but then if I fed the PWM through a CLC D-type latch I could synchronise it to the next NCO1 pulse which should leave me with the clean square wave I wanted.
     
    I nearly overlooked the gate function of Timer 2, it seems to be hidden in the description of the external reset source function.
     
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    oliverb
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    Re: PWM with a variable frequency timebase? 2019/05/25 01:10:25 (permalink)
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    If anyone else is interested: yes it worked. There are some limitations.
     
    Using an 8MHz crystal and PLL for 32MHz there is a practical speed limit. With the NCO pulse width set to 4 cycles if the frequency is set more than 6.4MHz the pulses will run together. Using a timer setting of 99 this gives a 64kHz limit. I can exceed this limit and get to 80kHz by turning off the final D-type, but there seems little benefit. I've got some 16MHz crystals.
     
    The TMR2 gate function appears to have a 1-cycle delay on it (the datasheet says 2 cycles). This can be offset by clocking the final d-type CLC on the trailing edge of the NCO1 pulse not the leading. This appears to prevent it from "anticipating" the timer. I'm a little concerned that future silicon revisions could "break" this.
     
    I suspect there may be a simpler way to achieve variable frequency and duty though.
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    NorthGuy
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    Re: PWM with a variable frequency timebase? 2019/05/25 16:53:05 (permalink)
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    What is wrong with simply varying the timer period?
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    mpgmike
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    Re: PWM with a variable frequency timebase? 2019/05/26 09:52:50 (permalink)
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    If you use NCO for frequency generation, you would have to determine the Period in relation to Timer 2, so that both are working with the same clock.  Feed NCO into an S-R CLC block SET.  The CLC output can then trigger a Timer 2 One-Shot (Mode 0b01001 from Table 22-1 of the Data Sheet), where T2PR is your Duty Cycle calculation.  Output from Timer 2 feeds your CLC S-R RESET.  Your Freq/DC% output would be the CLC_OUT.  Depending on how often you are changing Freq & DC%, it might become quite a bit of code overhead.

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