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Helpful ReplyHot!ADC on dsPIC33CK: pseudo-differential or 2 cores

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u741
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2019/04/07 14:49:31 (permalink)
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ADC on dsPIC33CK: pseudo-differential or 2 cores

Hello;
 
I'm interested in using the pseudo-differential ADC feature for a dsPIC33CK, as I need to measure an AC signal which has a "stable" reference ground at half of the Vdd.
 
1) In application note 70005213 (ADC), page 41, it says that for pseudo-differential mode (signed), the output signal will be between -1024 and 1023, which is 11 bit in total. Why is there not a 12 bit resolution, as for the single-ended (signed) mode?
 
2) As an alternative, I'm considering using 2 cores (triggered by same source, i.e. really sampling and converting perfectly simultaneously), one sampling (in single-ended mode) my signal and the other core sampling (in single-ended mode) the reference ground, and then in software I take the difference. In that case I end up with 12 bit (or even 13 bit if the signal would be a bipolar differential signal, which this mode could handle in contrast to the pseudo-differential mode).
 
Method 2) has much more error sources (since 2 ADC modules involved), but has  seems more accurate since 1 bit higher resolution (I still don't understand where the bit is lost for pseudo-diff mode). Is therefore method 2 preferred? Or has the pesudo-differential mode in practice any advantage in terms of error sources / noise despite the missing bit?
 
An even more tricky question: when using the inbuilt oversampling filter for both methods, it favors method 1) since there the oversampling result represents the average of differences whereas method 2) represents the difference of averages. Any comments to this?
 
What is the best way to measure my signal?
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JPortici
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Re: ADC on dsPIC33CK: pseudo-differential or 2 cores 2019/04/07 16:22:30 (permalink)
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I haven't tested the dsPIC33CK ADC in pseudodifferential mode. In the past i read that there were limitations on the samplerate, but never on the resolution. Maybte it's just a typo? Do you have a board with a 33CK? It's rather easty to test anyway...
 
Surely pseudodifferential mode has the advantage of being FASTER because you don't have to waste time conditioning the samples at each acquisition... at high samplerates it will be a huge penalty.
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u741
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Re: ADC on dsPIC33CK: pseudo-differential or 2 cores 2019/04/07 23:45:04 (permalink)
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it could be a typo in the table 70005213 (ADC), page 41, Table 4.1, as there is another, obvious, typo (for differential mode, the conditions given for max. and min. are not V_INP <> V_R+/-, but V_INP <> V_INN), but since even for the unsigned differential mode, the resolution is only given as 11 bit (max=3071 and min=1024, which would be weird values for a typo), I don't think it is a typo; i.e. it seems for pseudo-differential the resolution is really just 11bit (why??).
 
It would be good to understand how the pseudo-differential mode is implemented internally. Anyone knowing that?
 
Having to do the differential calculation in software is not a big problem in my case (in particular since I'm then able to handle even fully-differential signals), but I really wonder whether the overall ADC error would be better in the 11-bit hardware-implemented pseudo-differential mode than in the 12-bit software-implemented pseudo-differential mode.
 
Anyone having experience with these pseudo-differential modes?
 
If the sample rate could be reduced, as JPortici warns, could someone please confirm that for dsPIC33C devices? There is noting documented about that.
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Antipodean
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Re: ADC on dsPIC33CK: pseudo-differential or 2 cores 2019/04/08 05:34:35 (permalink)
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u741
1) In application note 70005213 (ADC), page 41, it says that for pseudo-differential mode (signed), the output signal will be between -1024 and 1023, which is 11 bit in total. Why is there not a 12 bit resolution, as for the single-ended (signed) mode?

 
How do you think the sign is indicated in the resulting value? Normally it is the MSB which is the 12th bit for this ADC.
 
Every ADC I have come across that can do signed or unsigned does this. You still get a 12 bit range from -1024 to 1023 so why do you think you are loosing resolution?
 

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Alan
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qhb
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Re: ADC on dsPIC33CK: pseudo-differential or 2 cores 2019/04/08 05:39:07 (permalink)
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Alan, as the OP stated, -1024 to 1023 is 11 bits, not 12.
 
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Antipodean
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Re: ADC on dsPIC33CK: pseudo-differential or 2 cores 2019/04/08 05:48:56 (permalink)
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qhb
Alan, as the OP stated, -1024 to 1023 is 11 bits, not 12.
 

 
1023 is hex 3FF which is 11 bits, plus the sign bit.
 
So the difference between -1024 and +1023 is 12 bits of ADC resolution.
 
Work out what a single ADC bit represents when doing a single ended or bipolar conversion over the same voltage range. You will 1LSB is the same for both formats.
 

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Alan
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Re: ADC on dsPIC33CK: pseudo-differential or 2 cores 2019/04/08 05:55:43 (permalink)
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Anti podean
qhb
Alan, as the OP stated, -1024 to 1023 is 11 bits, not 12.
 

1023 is hex 3FF which is 11 bits, plus the sign bit.

0x3FF = 0b0011 11111111
Looks like ten bits to me!
 
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du00000001
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Re: ADC on dsPIC33CK: pseudo-differential or 2 cores 2019/04/08 06:21:21 (permalink)
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Not the best day for our Anti-podeans today:
-1024..1023 is really an 11-Bit space.

PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)
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Antipodean
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Re: ADC on dsPIC33CK: pseudo-differential or 2 cores 2019/04/08 06:48:08 (permalink)
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du00000001
Not the best day for our Anti-podeans today:
-1024..1023 is really an 11-Bit space.




Argh, sorry, yes you are correct.
 
It is a while since I looked at this ADC. 
 
 

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Alan
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u741
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Re: ADC on dsPIC33CK: pseudo-differential or 2 cores 2019/04/08 09:10:48 (permalink)
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OK, People. Now the battle on basic base-2 integer mathematics is over. Let's bring back this thread to its original topic:
 
(1) why is the pseudo-differential ADC result (be it signed or unsigned) on a dsPIC33(C) limited to an 11 bit result space, even though the ADC and any result space in the regular modes is 12 bit??
 
(2) considering all the errors of an ADC incl. quantization error, noise, etc., do I get a more accurate result when (a) using the pseudo-differential mode (11 bit result) or (b) if I use two simultaneously sampling ADC cores (12 bit results each, but two non correlated quantization noise, etc.) with software-subtraction of the results?? (to me, this is not obvious).
 
Or two related questions:
(3) does someone know how the pseudo-differential mode works internally?
(4) is the pseudo-differential mode just a feature to make life easier for people with pseudo-differential signals; or is it actually a way to improve accuracy whenever you have pseudo-differential signals?
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Antipodean
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Re: ADC on dsPIC33CK: pseudo-differential or 2 cores 2019/04/08 14:26:44 (permalink)
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On point 4, it would be useful for sensors that use wheatstone bridge type circuits such as load cells.
 
 

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Alan
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u741
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Re: ADC on dsPIC33CK: pseudo-differential or 2 cores 2019/04/11 18:23:23 (permalink)
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I investigated this issue a bit further, and would like to communicate what I figured out:
 
- the pseudo-differential mode really is only 11 bit (+-1024 in signed mode). However, the result can be out of that +-1024 result space, which happens if ANNx is opposite of VDD/2 than the current signal. For instance: VSS=0; VDD=3.3 (VDD/2=1.65); ANNx=1.5V (allowed minimum), ANx=3.2V (i.e. (ANx-ANNx)>VDD/2) => result is +1055, since the full 12-bit space is still mapped between VSS and VDD. You really get values larger +1023 in the result register. I.e. Microchip solved the problem of needing "numbers outside +-2048" by cutting one bit (this is regrettable, of course).
 
- I assume the pseudo differential mode has some kind of switched capacitor structure which samples the ANx-ANNx voltage and then connects it with lower end to VSS or upper end to VDD, depending on sign of the voltage. In that case the result above makes sense.
 
- about accuracy: a differential signal which has large coupled "digital" noise (stdev 0.9-1.3 LSB on ANx and ANNx, if sampled separately in single-ended mode), really gets down the stdev to 0.2-0.3 in hardware pseudo-differential mode (you'd have to multiply that with a factor of 2 since you loose 1 bit resolution in that mode), whereas if you sample both channels separately and then do a software subtraction, you get a stdev of 1.4-1.6 on the subtraction result (i.e. more than factor 2 larger than stdev in pseudo-differential mode). I.e. the SNR of the conversion is better when using the hardware pseudo-differential mode, but since the signal resolution is reduced by a factor of 2, both options are still valid.
If you do the software-subtraction method from results of two synchronized ADC cores, the stdev of the subtraction result is down to 0.3-0.35 when using cores 0+1, i.e. that is the best result, since just minimally larger than the hardware pseudo-differential mode but you keep the 12 bit resolution. However I only could get that working for cores 0+1, I couldn't get rid of the correlated noise when synchronizing one of the dedicated cores with the shared core (I don't understand why I couldn't get that to work; perhaps there is some fundamental difference even though I gave the shared core clearly enough sampling time, delay the dedicated core, and have the same trigger source). I wish they hadn't removed two of the dedicated cores (compared to the 33E versions)
 
All stdev above are given for 10 kS/s (identical results also at 100 kS/s), with high-impedance inputs (~2kOhm) on jumper wires, to couple in some "noise".
 
In conclusion, if you have only to monitor 1 differential signal, you are better off in any case to do the subtraction by software and using synchronized cores 0+1. If you have more than 1 signal, the pseudo-differential is easier to implement, but if you are able to protect your inputs well from interference, perhaps the software-solution is still worth its additional bit.
 
Any comments welcome.
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u741
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Re: ADC on dsPIC33CK: pseudo-differential or 2 cores 2019/04/11 18:30:29 (permalink)
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I enclose a screenshot of the data: top shows individual conversion (AN0 on core0, AN1 on core1, ANN0 on core2 followed by ANN1 on core2); bottom shows pseudo-differential mode.
 
HOW DO I UPLOAD A PICTURE HERE?
 
 
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JPortici
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Re: ADC on dsPIC33CK: pseudo-differential or 2 cores 2019/04/12 02:08:02 (permalink)
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Don't. update somewhere else (gdrive/imgur/whatever) and add a link to the direct file
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u741
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Re: ADC on dsPIC33CK: pseudo-differential or 2 cores 2019/04/12 02:12:17 (permalink)
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attempt 1
https://ibb.co/TtQcMMC
post edited by u741 - 2019/04/12 02:23:38
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JPortici
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Re: ADC on dsPIC33CK: pseudo-differential or 2 cores 2019/04/12 02:23:11 (permalink) ☄ Helpfulby u741 2019/04/12 13:48:29
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there :) (right click -> view image)

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u741
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Re: ADC on dsPIC33CK: pseudo-differential or 2 cores 2019/04/12 02:28:47 (permalink)
5 (1)
thanks for help, JP.
 
some explanation:
- data on top (2 rows) showing the single ended data: AN0=core0, AN1=core1, ANN0+ANN1=core 2 sequentially. Cores 0+1+2(for first conversion) are synchronized (but core 2 doesn't seem to be synchronized, though I believe I did everything right). In the bottom row, the software-subtraction results are shown (and also, for comparison, the difference core0-core1, which is successfully synchronized and very low noise).
 
- data in bottom figure is the direct hardware pseudo-differential data of AN0 and AN1.
 
the noise data (standard deviations) given to the left in the text part.
 
 
perhaps useful for some of you when having to make decisions about which mode to choose.
 
#17
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