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Hot!How to setup PIC10F322 CLC Module in Flip-Flop mode?

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rbuck
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2019/04/06 10:26:05 (permalink)
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How to setup PIC10F322 CLC Module in Flip-Flop mode?

PIC10F322
MPLAB X v5.10

I'm trying to use the CLC module as a 1-Input D flip-flop with S and R. I want to divide a 200 Hz input signal by 2 to get 100 Hz out. I'm not having any luck.

I have Gate 1 setup for an input from CKCIN2 which is RA2 on the PIC. I have RA2 setup as an input in the TRIS register. I have Gate 2 set to CLC1. I'm assuming this is the output of the CLC module as there is no CLCOUT in the drop down list of the CLC Easy Setup tool. I have the input setup as being inverted. I have also tried it with the input not inverted. I have Gate 3 setup as an inverted output but no input as I leave the 4 inputs grounded. This should result in R being high. I have no setup for Gate 4 which should result in S being low.

My scope shows a 4.5 volt, 200 Hz square wave into pin RA2. Pin RA1 is the CLC1 output according to the pin diagram in the pin manager of MCC. All I see on RA1 is a 350 mV, 200 Hz signal instead of the ~5 volt, 100 Hz signal I would expect.

I have a LED attached to RA0 so I can determine where I get to in my code. The bsf  LATA, 0  statement turns the LED on. If I keep my signal generator turned off, the LED turns on, indicating I reach that point in the code. When I turn the signal generator on, the LED turns off.

Code is attached.
#include "p10f322.inc"
    
; CONFIG
 __CONFIG _FOSC_INTOSC & _BOREN_OFF & _WDTE_OFF & _PWRTE_ON & _MCLRE_ON & _CP_OFF & _LVP_OFF & _LPBOR_OFF & _BORV_LO & _WRT_OFF

RES_VECT CODE 0x0000 ; processor reset vector
    GOTO START ; go to beginning of program
    
temp1 equ 0x40
temp2 equ 0x41

MAIN_PROG CODE ; let linker place main program
    radix dec ;default to decimal numbers
 
START
    movlw 0x70
    movwf OSCCON ; set oscillator to 16 MHz
    CLRF TRISA ; all pins are outputs
    CLRF LATA ; clear all latches
    CLRF ANSELA ; all pins digital
    CLRF WPUA ; disable weak pull-ups
    ;bsf TRISA, 0 ; RA0 is an input
    bsf TRISA, 2 ; RA2 is an input
    
    ; setup TMR0
    movlw 0x88 ; External clock on RA2, , rising edge, no prescale
    movwf OPTION_REG
    
    ; setup CLC module, input on RA2, Flip-Flop output on RA1
    movlw 0xC4 ;0xC4
    movwf CLC1CON ; D Flip-Flop, port pin output enabled, module enabled
    movlw 0x02
    movwf CLC1GLS0 ; gating OR, no inversion
    movlw 0x04
    movwf CLC1GLS1
    movlw 0x00
    movwf CLC1GLS2 ; gating OR, no inversion
    movlw 0x00
    movwf CLC1GLS3
    movlw 0x04
    movwf CLC1POL
    movlw 0x02
    movwf CLC1SEL0
    movlw 0x00
    movwf CLC1SEL1

Loop1:
    movlw 0xFF ; decimal 255 - POINT A
    movwf temp1
    movlw 0x0C; decimal 12
    movwf temp2
    
Loop2:
    decfsz temp1, 1
    goto Loop2
    decfsz temp2, 1
    goto Loop2
    
    movlw 1<<LC1G2POL ;toggle flipflop D input
    xorwf CLC1POL
    bsf LATA, 0
    goto Loop1 ; POINT B - time from POINT A to POINT B is 2.3 msec
    
    END

Any suggestions are appreciated.
 
#1

6 Replies Related Threads

    davekw7x
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    Re: How to setup PIC10F322 CLC Module in Flip-Flop mode? 2019/04/06 13:44:16 (permalink)
    +1 (1)
    rbuck
    ...All I see on RA1 is a 350 mV, 200 Hz signal instead of the ~5 volt, 100 Hz signal I would expect.

    That's bleed-through (maybe noise or ground noise between circuit and 'scope or something).  Your software is not generating CLC output.
     
    rbuck
    ...suggestions...



    I don't use Assembly Language enough to give a critique of the entire project, so I'll not comment on anything in your code except for the CLC stuff.  (I do appreciate your showing us everything.  A somewhat rare treat.)

    [/Begin disclaimer]
    Not tested.  (See Footnote.)
    [/End disclaimer]

    Hmmm...
    Having been interested in manual configuration of CLC modules ever since the demise of the late, great, CLCDesignerTool, I decided to de-construct your CLC statements.

    I think that this is the Bad Boy:

        movlw 0x04
        movwf CLC1POL

     Instead of describing the connections, I used MCC in MPLABX to show them.  I found that I can easily use MCC with "toy projects" for intricate stuff like this even if the actual project is not MCC-generated.  (Way to go, MCC-CLC guys!)

    The first image, CLC1_Bad.png shows, I think, what you set up.  (MCC-generated C code is attached as CLC1_Initialize_Bad.c;  I think that one is equivalent to your assembly statements).  Note that the CLC window of MCC identifies the RA2 input as CLCIN2

    The inverted output of the undriven OR gate 3 is logic 1, so that the DFF is held reset.  (The generated file has CLC1POL = 4, which is the same as your assembly statements.)

    Now, by removing inversion of OR gate 3, it looks more like what I would expect to implement the toggle functionality, and the generated file has CLC1POL = 0x00, which is, I think, correct  The other attachments are the results with this change.

    Bottom line:
    Try the change and tell us what happens.

    Regards,

    Dave

    Footnote:
    Donald Knuth
      Beware of bugs in the above code; I have only proved it correct, not tried it.

    post edited by davekw7x - 2019/04/06 14:31:17

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    #2
    rbuck
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    Re: How to setup PIC10F322 CLC Module in Flip-Flop mode? 2019/04/06 16:26:31 (permalink)
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    Dave, you are correct, your first image is what I had configured. I changed it to what you suggested but get the same results. I have tried virtually every configuration possible with the same results.
     
    As a side note, the OR gate, NOR gate, and the AND gate functions all work. The only one that doesn't work is the Flip-Flop. I'm starting to think there is a silicon issue.
     
    The CLC tool is available in MCC if you check the Project Resources Window. That is what I used to get the settings I had. I had R set high but had previously tested it being set low as you show. Microchip doesn't document (at least I couldn't find it) what states are required for the R and S inputs.
     
    I have a PIC12F1501 that I am going to try. Maybe I can get the Flip-Flop to work in that part.
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    qhb
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    Re: How to setup PIC10F322 CLC Module in Flip-Flop mode? 2019/04/06 16:48:18 (permalink)
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    rbuck
    ...
     Microchip doesn't document (at least I couldn't find it) what states are required for the R and S inputs.

    Disclaimer, I've never used these tools.
    Most "logic design" software uses positive logic on the pins.
    Most real chips use negative logic on inputs like "R", and "S".
    I'd assume R and S are activated by a positive signal if you don't find any documentation saying the opposite.
     
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    davekw7x
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    Re: How to setup PIC10F322 CLC Module in Flip-Flop mode? 2019/04/06 18:43:38 (permalink)
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    rbuck
    ...I'm starting to think there is a silicon issue...

    When I said "not tested" on my previous post, I meant that I had not specifically tested this function on this chip today.  I have used the DFF from MCC-based CLC modules on a number of PIC16 and PIC18 projects.  Never had a problem related to the DFF.
     
    But to eliminate any nagging doubts...
    I went back to an old Solderless Breadboard that I had set up for a PIC10F322 and ran the project that I had used to generate the attachments in my previous post.
    The frequency generator that was closest to my workspace only goes down to a little more than 100 kHz.  I used 200 kHz for this test and found a 100 kHz square wave on Pin 4 of the '322.
     
    Setup:
    • PIC10F322 in DIP-8 package, operating at 3.3V with 16 MHz internal clock.
    • MPLABX version 5.15, MCC plug-in version 3.75
    • XC8 version 2.05 in C90 mode, optimization level 2.
    • PICKit3 reports Device Revision ID = 2
     
    Project is attached.  For the attached image: Top trace is signal generator to '322 CLC input, bottom trace is CLC output.  Noise on signal generator signal is due to quickie setup without terminating end of coax from generator.
     
    Bottom line: Works as advertised with the C language project.  Can't (won't) try to look at ASM code.  (The C project takes a total of 39 words program memory and 2 bytes of data memory.)
     
    Regards,
     
    Dave
    post edited by davekw7x - 2019/04/06 20:19:53

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    rbuck
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    Re: How to setup PIC10F322 CLC Module in Flip-Flop mode? 2019/04/06 20:40:08 (permalink)
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    qhb, thanks for confirming that. I sort of figured that was the logic by looking at a CD74HCT74 part. Both R and S have to be high for the clock to have any effect.

    davekw7x, thanks for taking time to actually test the hardware. I will make the changes to my ASM code tomorrow. If it doesn't work, I will change to C. I tend to use ASM when I am working with the 10F parts. I use C for all other MCHP projects. This is the first time I have used ASM in a couple of years. It took a little while to recall the syntax and quirks.

    I will let you know what the final result and solution is tomorrow. I appreciate your help.

    Ray (AB7HE)
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    rbuck
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    Re: How to setup PIC10F322 CLC Module in Flip-Flop mode? 2019/04/07 17:10:15 (permalink)
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    Dave,
    I got both the C and the ASM versions working. It turned out the real problem was with the drive level coming out of my signal generator. I have a Tektronix AFG3021B. Even though the output level is set to 5.000 volts, my scope only shows 2.36 volts out on the TTL jack.
     
    I ended up using the generator to drive a 74LS06 inverter which I then used to drive the PIC. Once I did that, everything started working as it should. I don't know why that level was sufficient to drive the OR, NOR, and AND gates hard enough for them to work.
     
    Attached is a screen shot of my scope screen showing 200 Hz in and 100 Hz out.
     
     
    What I actually wanted to do with the PIC was to use it to divide by different values such as 10 or 20. The divide by 2 was just a starting point to get familiar with the CLC module. I figured I could use Timer0 and clock both it and the CLC module with the input signal. I would load TMR0 with a value of 1/2 of the divide count I needed. If I needed to divide by 10, I would load TMR0 with 250 (-5 decimal) I would sit in a loop just checking for the TMR0 roll over. Then I would toggle the polarity of the D-input to 0 so it would ignore the next pulse and reload TMR0 with the count.
     
    Unfortunately that won't work with a PIC10F322. When you enable the CLC module, RA2 cannot be used as an external input for TMR0. The CLCIN2 input takes precedence over the TMR0 clock input. The precedence table doesn't show this but my testing confirms that is the way it works. If you assign CLCIN1 to the Flip-Flop, the PIC ignores the TMR0 signal.
     
    If you close the MCC tool and re-open it with RA0 assigned as the CLC input and RA2 assigned as the TMR0 clock input, it pops us a warning: "Cannot deselect CLCIN2 as some of the CLC1 input muxes are configured to it."
     
    I have a couple of PIC12F1501 chips that may work. The 1501 has 2 CLC modules. Hopefully I can use the CLC2 module for the input signal. I should then be able to use the T0CKI input for TMR0 since the CLC1 module would not be enabled. Microchip is using double-speak in the documentation as to whether this will work or not.
     
    They say this:
    Each stage is setup at run time by writing to the corresponding CLCx Special Function Registers. This has the added advantage of permitting logic reconfiguration on-the-fly during program execution.

     
    Then they say this:
    The following steps should be followed when setting up the CLCx: Disable CLCx by clearing the LCxEN bit.

     
    The question is what happens when you shut the module down? When you re-enable it, will it recover fast enough to pick up the next rising edge pulse?
     
    Edit: ASM version used 33 words program memory and 0 bytes data memory.
    post edited by rbuck - 2019/04/07 18:12:01

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