...All I see on RA1 is a 350 mV, 200 Hz signal instead of the ~5 volt, 100 Hz signal I would expect.
That's bleed-through (maybe noise or ground noise between circuit and 'scope or something). Your software is not generating CLC output.
I don't use Assembly Language enough to give a critique of the entire project, so I'll not comment on anything in your code except for the CLC stuff. (I do appreciate your showing us everything. A somewhat rare treat.)
Not tested. (See Footnote.)
Having been interested in manual configuration of CLC modules ever since the demise of the late, great, CLCDesignerTool, I decided to de-construct your CLC statements.
I think that this is the Bad Boy:
Instead of describing the connections, I used MCC in MPLABX to show them. I found that I can easily use MCC with "toy projects" for intricate stuff like this even if the actual project is not MCC-generated. (Way to go, MCC-CLC guys!)
The first image, CLC1_Bad.png
shows, I think, what you set up. (MCC-generated C code is attached as CLC1_Initialize_Bad.c; I think that one is equivalent to your assembly statements). Note that the CLC window of MCC identifies the RA2 input as CLCIN2
The inverted output of the undriven OR gate 3 is logic 1, so that the DFF is held reset. (The generated file has CLC1POL = 4, which is the same as your assembly statements.)
Now, by removing inversion of OR gate 3, it looks more like what I would expect to implement the toggle functionality, and the generated file has CLC1POL = 0x00
, which is, I think, correct The other attachments are the results with this change.
Try the change and tell us what happens.
Beware of bugs in the above code; I have only proved it correct, not tried it.
post edited by davekw7x - 2019/04/06 14:31:17