PIC18F ECAN: Tx buffer registers locked during transmit?

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SpokaneNexus
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2019/03/24 09:03:58 (permalink)
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PIC18F ECAN: Tx buffer registers locked during transmit?

I'm presently working with a PIC18F26K80 and its ECAN module's three transmit buffers in Mode 0. It appears that when a given transmit buffer has been enabled for transmission (TXBnCONbits.TXREQ = 1) its associated SFR's become read-only. The SFR's of the other two Tx buffers remain writable even when the third is "locked" in this way. However, I can't find any confirmation of this in the spec sheet.
 
No, I don't want to modify the registers when they might be being used for a transmission. And yes, this does make sense from a design standpoint. But I'm surprised that it doesn't appear to be documented. It makes me wonder if there's another side effect that DOES matter. Thus I'd like to see documentation on it.
 
Anyone else 1) seen this, and more importantly 2) know if/where it's documented?
 
Thanks!
post edited by SpokaneNexus - 2019/03/24 09:04:59
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    SpokaneNexus
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    Re: PIC18F ECAN: Tx buffer registers locked during transmit? 2019/03/24 10:14:32 (permalink)
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    Found it. In the discussion of TXBnCON (section "Register 27-5" of the spec sheet), footnote 2 says "While TXREQ is set, Transmit Buffer registers remain read-only." Section 27.5.4 also says "As with all transmit buffers, once the TXREQ bit is set, buffer registers become read-only and any writes to them will be ignored". No mention of other side effects, so presumably it's literally just that: The registers associated with the transmit buffer in question become read only.
     
    Posting this answer in case someone else searches on this same question.
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