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Helpful ReplyHot!dsPIC33CK ADC triggering-by-SCCP issue

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u741
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2019/02/14 05:44:11 (permalink)
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dsPIC33CK ADC triggering-by-SCCP issue

Hello all, I would need some quick help for a seemingly simple problem.
 
I'm trying to trigger the ADC shared-core of a dsPIC33CK256MP508 by the SCCP4 in 32bit timer mode, for periodically converting AN13 and AN16. Should be possible according to the SCCP/MCCP reference manual DS33035A, which explicitly states that the 32bit timer mode can be used for ADC triggering. I did not find any other information in the device-specific data sheet sections either.
 
The ADC configuration is correct and working, since, if I use "common software triggering" (ADTRIGxx = 1 for ch13 and ch16), both channels convert (AN13RDY and AN1616RDY bits set, and ADCBUFxx have plausible results), whenever the software creates the manual trigger by setting the ADCON3L.SWCTRG bit.
 
Also, the SCCP4 seems to be set up correctly; I checked that it counts and that it periodically resets as intended.
 
But the ADC doesn't start (ANxxRDY flags never set; ADCBUFxx stay 0) when triggering it from the SCCP4 (by setting ADTRIG3L = 0x1700 and ADTRIG4L = 0x0017).
 
Where is the missing link between SCCP and ADC? Or what else did I miss?
 
below the source code for ADC and SCCP setup. If you have done something similar, please check the code or send me a code example which works. Your help is appreciated!
 
/////// SET UP OF ADC SHARED CORE, AN13 AND AN16
ADCON1L = 0; // stop and clear any previous configuration (unnecessary, since after reset)
// Configure the I/O pins
ANSELCbits.ANSELC1 = 1; // AN13
TRISCbits.TRISC1 = 1;
ANSELCbits.ANSELC7 = 1; // AN16
TRISCbits.TRISC7 = 1;
// ADC config: ADC clock source is Fp=Fosc/2;
ADCON1H = 0x0060; // 12 bit result resolution for shared core, and integer data format
ADCON2L = 0; // shared-core clock divide to 1:2, i.e. 2 source clock periods (T_CORE_SRC) for a shared core clock period (T_ADCORE)
// select shared-core sampling time as multiple of T_AD_CORE
ADCON2H = 8; // 8+1 = 10 cycles sampling 0x4e
// Configure the ADC references
ADCON3L = 0x0000; // V_REFH = AVDD V_REFL = AVSS; SWLCTRG (software level sensitive) off
// Select the common ADC clock source, configure the prescaler, and switch the used cores on/off
ADCON3H = 0x0300; //0x0000 // clock is Fp; clock divider is 1:4 (3+1); only shared ADC core on
// single/differential input configuration, and output format for each channel
ADMOD0Hbits.SIGN13 = 0;
ADMOD0Hbits.DIFF13 = 0;
ADMOD1Lbits.SIGN16 = 0;
ADMOD1Lbits.DIFF16 = 0;
// set the warmup time
ADCON5Hbits.WARMTIME = 8; // 256 source clock periods warmup
// activate the ADC module
ADCON1Lbits.ADON = 1;
// Turn on the module power for the cores to be used
ADCON5L |= 0x0080; // shared-core power on; dedicated cores off
// Poll until power ready
while (ADCON5Lbits.SHRRDY == 0)
;
// enable the cores to be used
ADCON3H |= 0x0080; // only shared core enable
// triggers set to edge sensitive (not needed after reset)
ADLVLTRGL = 0x0000; // input trigger is edge sensitive for channel 13
ADLVLTRGH = 0x0000; // input trigger is edge sensitive for channel 16
// set the trigger sources
ADTRIG3L = 0x1700; // trigger for channel 13: SCCP4
ADTRIG4L = 0x0017; // trigger for channel 16: SCCP4
//ADTRIG3L = 0x0100; // trigger for channel 13: common software (test purpose only)
//ADTRIG4L = 0x0001; // trigger for channel 16: common software (test purpose only)
 
//////////// SET UP OF SCCP4
// using SCCP4 for triggering the shared ADC
CCP4CON1L = 0x0060; // clock is Fp=Fosc/2 (64MHz); prescaler 1:2, 32bit mode; timer mode
CCP4CON1H = 0x0000;
CCP4CON2L = CCP4CON2H = CCP4CON3H = CCP4STATL = 0; // not needed since after reset
CCP4PRH = 0x0004; CCP4PRL = 0xe200; // period is 320 000, i.e. 100 Hz
CCP4CON1Lbits.CCPON = 1; // switch timer on
IFS2bits.CCP4IF = 0; // not needed since after reset

///////////////////////////////////////////////////

 
#1
IACooper
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Re: dsPIC33CK ADC triggering-by-SCCP issue 2019/02/14 06:12:21 (permalink)
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Hiya,
I had a similar problem triggering the ADC using CCP1 special function trigger on the dsPIC33CK128MP205.  I raised a support ticket which resulted in M'Chip agreeing it didn't work for them either.  It then progressed further before the response I got back was that it seemed it had been a "typing mistake" in the datasheet to say that it would work, and that this feature is not supported.   Clearly it was a "typing mistake" in multiple places.
 
The best alternative they could suggest, and which I have found does work, is to use the peripheral trigger generator to trigger the ADC instead.  This obviously isn't much help if you want to trigger multiple ADC channels by multiple timers at different rates,  but it's worked for my simple needs.
 
Ian.
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u741
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Re: dsPIC33CK ADC triggering-by-SCCP issue 2019/02/14 08:02:30 (permalink)
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Hello Ian,
 
many thanks. Glad to hear that it was not my incompetence to get this working, but an obvious silicon bug of these new and interesting devices ("typing mistake"? no way, since the ADC triggering option by SCCP is clearly described both in the SCCP documentation and in the device-ADC documentation, and they have reserved so many trigger channels for it).
 
I wonder now which of the trigger sources in the documentation (device data sheet page 313) are working? If the 8 SCCP/MCCP are not working, are the 16 PWM triggers not working either? are the 2 CLC triggers working? Or is only the PTG working?
 
It would be nice if they could address that in an errata sheet; and hopefully they will revise this in a further silicon release.
 
I'll try now to trigger it via SCCP -> virtual port -> ADTRG31(PPS input); that hopefully works (assuming the ADTRG31 trigger works). But, as you wrote, this alternative only allows you to trigger all channels simultaneously, not individually which would have been possible with linking the individual ADC channels to different SCCPx.
 
Such a pity that they messed up with implementing this interesting feature ... let's hope for the next silicon revision ...
 
I also shortly played with the "level software trigger" (continuous conversion as long as level is high), which I didn't get to work either (but didn't try extensively), so there might also be a silicon errata there, in case someone doesn't get this to work either.
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IACooper
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Re: dsPIC33CK ADC triggering-by-SCCP issue 2019/02/14 09:01:16 (permalink)
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I can only pass on how it was described to me, but I also feel it's an impressive level of typing mistake! wink: wink
 
Whilst awaiting feedback on the support ticket I was using the CCP timer to generate a CCP interrupt, then in the service routine for that I was giving a software trigger to the ADC.   Obviously this does have an overhead in terms of processor cycles associated with it, but may be an acceptable way of triggering for some.
 
I did wonder if it would be possible to use one of the CLC modules as a 'pass through', using the aux. signal from the CCP timer to feed into the CLC block and then passing the signal straight through that to trigger the ADC.  It isn't something I actually tried, as with a bit of head scratching and studying of the datasheet I managed to get the PTG working and triggering at the right rate, which means I can do away with timer interrupts.
 
...I still have an outstanding ticket over DMA overrun interrupts whilst moving data out of the ADC, which again support have confirmed seems to be an issue, but they are currently investigating further.
 
In brighter news, when I ran into the problem of the AGC and Noise Suppression library functions not being compiled to work with dsPIC33C*  series micros,  tech. support have recompiled them for me and sent them (untested).  My initial findings suggest they are working on my "C" series micro as well  Smile: Smile
 
They certainly seem interesting and nice devices, although can be a bit frustrating at times trying to work out why things don't appear to be working!
 
IC.
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u741
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Re: dsPIC33CK ADC triggering-by-SCCP issue 2019/02/14 15:19:19 (permalink)
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I tried now: SCCP(output compare)->virtual port->ADTRG31, and that works (but, in contrast to the not working direct-SCCP triggering concept, all channels can only be triggered by the same single SCCP).
 
In conclusion, ADC triggering works for the current dsPIC33CK256MP508 devices (tested for shared-core ADC only):
- common software trigger: YES
- level software trigger: perhaps not (but didn't try hard enough)
- SCCP trigger: NO (neither 16 nor 32 bit)
- PWM trigger: NO (didn't try too hard either, but since based on SCCP, I don't think it would work)
- CLC: not tested
- PTG: YES (tested by Ian)
- ADTRG31: YES
 
I'm sure the software solution outlined by Ian (SCCP interrupt routine triggering the common software trigger) works also, but that is waste of CPU if you have such powerful periphery, and also here all AD-channels could only be triggered by the same SCCP.
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BLmicro
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Re: dsPIC33CK ADC triggering-by-SCCP issue 2019/02/18 16:04:15 (permalink)
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I tried to get PWM to trigger an ADC on the 33CH and could not get it to work.
 
There was a great post by Mysil on another thread explaining how they bring these peripherals together when they come out with a new device, some even developed at other places and how they sometimes don't play well with each other or as the marketing guys dreamed they would. It was very interesting.
 
-BL
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IACooper
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Re: dsPIC33CK ADC triggering-by-SCCP issue 2019/02/19 02:07:14 (permalink)
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BLmicro
...There was a great post by Mysil on another thread explaining how they bring these peripherals together when they come out with a new device, some even developed at other places and how they sometimes don't play well with each other or as the marketing guys dreamed they would. It was very interesting.



Perhaps I'm being unfair, but having produced a prototype it would be nice if it could be tested and issues found and resolved before advertising and shipping the new product openly to customers.  No doubt testing every last detail and combination of every feature is one heck of a lot of work, but in terms of the ADC module there are x30 different triggers selectable, of those x23 (76%) of them are apparently "typing mistakes" - really?
#7
BLmicro
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Re: dsPIC33CK ADC triggering-by-SCCP issue 2019/02/27 09:46:03 (permalink)
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I get the feeling that since the devices have so many peripherals that they feel there are 2-3 ways to do a work around and accomplish the same functionality. Where this might be true, revisiting code to upgrade it when a solution comes around often never happens or it gets built on with so many layers that you're afraid to change it after a while.
 
I'm finding that the shared ADC core on the 33CH slave core doesn't appear to work. It functions as described but the results are as if something is not connected (no change in value). Same code on the master core works flawlessly. Starting another thread on this issue alone.
 
-BL
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Joon
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Re: dsPIC33CK ADC triggering-by-SCCP issue 2019/03/15 09:11:00 (permalink) ☄ Helpfulby IACooper 2019/03/18 08:57:41
4 (2)
I am a dspic33ch user and believe its core is the same with dspic33ck.
I also had the same problem,but managed to work it properly using sccp interrupt.
The key point in this problem is how user generates sccp interrupt.
 
In sccp module, I generate 2 interrupt.
SCCP1 interrupt : timer interrupt (mod = 0)
SCCP2 interrupt : Dual Edge compare mode, buffered (mod = 0b0101)
 
In ADC module, the results are 
ADC : triggered by SCC1 interrupt : Not working
ADC : triggered by SCC2 interrupt : working.
 
In a ADC document, it describes one of TRGSRC as "Master SCCPx PWM interrupt", so normal timer interrupt of SCCx does not work and should be PWM-type interrupt I think.
 
Hope this information is useful for your tests.
#9
phill_
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Re: dsPIC33CK ADC triggering-by-SCCP issue 2019/05/28 02:49:21 (permalink)
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Hello,
 
I am experiencing the same issue as described above, but also with:
Dual Edge compare mode, buffered (mod = 0b0101) it does not seem to work.
 
Has somebody else been able to find a way to get it working anyway?
Or do i have to use the PTG.
#10
Ovollyn
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Re: dsPIC33CK ADC triggering-by-SCCP issue 2019/07/22 06:51:22 (permalink)
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Thank you Joon,

I was searching for a solution here:

https://www.microchip.com/forums/m1105702.aspx

Your answer really helped me. Now my system seems like to work !

M
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