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Hot!PIC32MM CLC documentation

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al_bin
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2019/02/08 06:14:23 (permalink)
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PIC32MM CLC documentation

 
The CLC in the PIC32MM0256GPM028 processor works, but the data sources are completely incompatible with the documentation.
For the tested processor (rev2) in the SSOP28  housing, for example
According to datasheet:
DS3 <2: 0>: Data Selection MUX 3 Signal Selection bitsFor CLC1:
111 = Unused // tested OCM5
110 = MCCP1 OCMP compare match event // tested OCM4
101 = DMA Channel 0 interrupt // tested OCMP4 OUT
100 = ADC end of conversion
011 = UART1 TX out // tested SDO1
010 = CMP1 out // tested CMP2
001 = CLC2 out // tested CLC1
000 = CLCINB I / O pin // tested CLCINA

DS1 <2: 0>: Data Selection MUX 1 Signal Selection bitsFor CLC1:
111 = SCCP5 OCMP compare match event // Tested MCCP1
110 = MCCP1 OCMP compare match event
101 = RTCC event // tested MCCP1
100 = CMP3 out // tested REFCLK
011 = SPI1 SDI1 in // tested LPRC
010 = SCCP5 OCM5 output
001 = CLC2 out // tested PBCLK
000 = CLCINB I / O pin // tested CLCINA

Anyone have any Microchip data on this topic?
Anyone can verify these observations ?, In other packages/memory variants ?,
Has data from other MUX/CLC instances?
 


Albert
post edited by al_bin - 2019/02/08 06:23:54
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2 Replies Related Threads

    crosland
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    Re: PIC32MM CLC documentation 2019/02/08 07:30:14 (permalink)
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    I would suggest raising a support ticket, then report back here with the response.
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    cvm
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    Re: PIC32MM CLC documentation 2019/02/08 10:27:57 (permalink)
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    You could be right, but your DS3 results match DS2, so possibly check if you are getting to the right bits in CLCxSEL. Also. a 28pin qfn and a 28pin ssop have pin numbers that do not match (shifted by 3), if you are using the qfn table in the datasheet to determine your pins, your pps/rpn will be incorrect also.
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