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hblmerleg
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2019/01/31 10:04:00 (permalink)
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Strange INT timing

Hi Everyone
 
I tried to find out a problem for long long days without result. May be someone has the same.
 
I have an ADC with SPI. I use 1200 sample/sec. I use DMA with 2 CH. It works well until I enable the RTC IC on I2C. After enabling sometime the sample/second value goes up to ~40000. The DMA transfer starts with Change Notification, INT priority 5. This is the only interrupt on this level. The DMA block complete (SPI RX) interrupt is on level 6, this is the only interrupt on this level also. 
I can't figure out what is modifying the timing of the interrupt. 
 
Any idea?
#1

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    Larry.Standage
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    Re: Strange INT timing 2019/01/31 10:58:32 (permalink)
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    Hard to tell without a little more information.
    • Which processor?
    • Are you using Harmony?
    • How often is traffic happening on the I2C?
    • Is the I2C handling done through an interrupt? What level is that interrupt?
    Off-hand, it seems to me that the the main reason for the speedup would be if the processor couldn't clear the CN interrupt, because it was busy with something else, probably I2C related. If something in the I2C code prevents the interrupts from being handled, then the DMA could be retriggered over and over because the CN interrupt doesn't clear itself.
    If you have an available DMA channel, what you might do is chain it to the one handling the ADC, and have it read the PORT that has the CN turned on. Then the interrupt should always be cleared, and the processor doesn't have to deal with it. 
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    hblmerleg
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    Re: Strange INT timing 2019/02/01 04:39:49 (permalink)
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    Thank you the answer. I use pic32mz0512efe144, no harmony, no libs.
     
    The additional DMA CH is a good idea. But only the falling edge of the signal is need to start the DMA transfer. (I tried the EDGEDETECT mode but there is minimal documetation about it and it did not work well).
     
    I moved the Sample/Second calculation from the DMA recieve complete interrupt to CN interrupt. Now the calculated value is always correct. I thing something is happening in the DMA. Anyway the datas from the ADC are without any error in millions of transactions.
     
    So it seems it solved.
    #3
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