Hot!dspic33CK - ADC channel coupling behavior (for higher impedance sources)

Page: 12 > Showing page 1 of 2
Author
cbarn
Starting Member
  • Total Posts : 50
  • Reward points : 0
  • Joined: 2007/01/20 11:02:14
  • Location: 0
  • Status: offline
2019/01/27 20:58:33 (permalink)
0

dspic33CK - ADC channel coupling behavior (for higher impedance sources)

On the shared core, I've configured several channels to be sampled on the same trigger.  On the 33C, the channels are automatically sampled lowest to highest and placed into their respective ADBUF registers.  In this case the trigger list includes channels 12 and 14.  Channel 14 has a DC impedance of 45kohm, buffered w/390pF.  [See note and EOM]

As the voltage on channel 12 is varied from 0 to 3.3 - the ADC reading on channel 14 varies proportionally totaling 4%.
 
As I understand it, the ADC input model is 500nA of leakage and 344 ohms to a fully discharged Chold of 5pF.  (see attached)
 
With Chold fully discharge, there *shouldn't* be any cross coupling despite the 'high' impedance of the source.
 
Did I misunderstand the model, is the datasheet inaccurate, or some 3rd thing?
[There are no ADC issues in the errata DS8000796B]
 
----------------
This circuit has low *impedance* as required - DC impedance is high, but AC impedance is low.  Sample rate is low enough for the 390pF to fully recharge.  Based on the analog input model the expected error due to the source impedance is 1.3% +-0.7%.
 
post edited by cbarn - 2019/03/26 15:26:44

Attached Image(s)

#1

24 Replies Related Threads

    cobusve
    Super Member
    • Total Posts : 464
    • Reward points : 0
    • Joined: 2012/04/02 16:15:40
    • Location: Chandler
    • Status: offline
    Re: dspic33CK - ADC channel coupling behavior 2019/01/27 22:44:59 (permalink)
    0
    How are you fully discharging CHold? You would have to leave CHold connected to Vss for long enough to accomplish this, perhaps you are not meeting the time requirement?
     
    If there remains a voltage on CHold from the prior conversion it would cause exactly what you are describing ...

    Also take a look at https://www.microforum.cc/ - a great resource for information on PIC and AVR microcontrollers and embedded programming in general. You can also post questions to the experts there.
    #2
    cobusve
    Super Member
    • Total Posts : 464
    • Reward points : 0
    • Joined: 2012/04/02 16:15:40
    • Location: Chandler
    • Status: offline
    Re: dspic33CK - ADC channel coupling behavior 2019/01/27 22:54:13 (permalink)
    0
    Forgot to ask. If you make it sample multiple times (like 10x) after the channel switch on the new channel, do you see the value improve from sample to sample? If it does this is a sure sign that you have a residual DC voltage on the CHold cap which needs to be removed OR you need to increase the sample charge time (acquisition time) to reduce the coupling.
     

    Also take a look at https://www.microforum.cc/ - a great resource for information on PIC and AVR microcontrollers and embedded programming in general. You can also post questions to the experts there.
    #3
    du00000001
    Just Some Member
    • Total Posts : 2549
    • Reward points : 0
    • Joined: 2016/05/03 13:52:42
    • Location: Germany
    • Status: offline
    Re: dspic33CK - ADC channel coupling behavior 2019/01/28 01:26:15 (permalink)
    0
    @ cbarn
    cbarn... DC impedance is high, but AC impedance is low. ...

    Might be you do not understand how an ADC is working, might be there's another issue.
    Would be nice if you provided 2 things about the circuit @ channel 12:
    • Schematics of the signal path
    • A description of the signal to be digitized: waveform, offset, frequency, ...

    PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)
    #4
    cbarn
    Starting Member
    • Total Posts : 50
    • Reward points : 0
    • Joined: 2007/01/20 11:02:14
    • Location: 0
    • Status: offline
    Re: dspic33CK - ADC channel coupling behavior 2019/01/28 06:55:18 (permalink)
    0
    du00000001
    @ cbarn
    cbarn... DC impedance is high, but AC impedance is low. ...

    Might be you do not understand how an ADC is working, might be there's another issue.
    Would be nice if you provided 2 things about the circuit @ channel 12:
    • Schematics of the signal path
    • A description of the signal to be digitized: waveform, offset, frequency, ...

    The system's purpose is a battery charger so Vout is expected to be connected to a battery, however - in the absence power elsewhere in the, power is consumed at Vout to run the system.  That is the present state. 
    Vout and Vin are the input and output to a sync buck converter (bidirectional so actually a buck or boost in reverse), these AN channel are the voltage sense signals.  During this testing, a timer is generating timing for ADCs, but the half bridges are off.  Vout is connect to a power supply (for stiffness) and Vin is a diode drop lower due to the half-bridge body diode.  Both Vout and Vin have >10uF of ceramics and >3300uF of electrolytic capacitance.

    The ADC channel assignments and sample rate in this experiment
    0 - ISNS  (25khz)  (dedicated core)
    1 - ISNS (25khz)   (dedicated core)
    2 - POT1      (25khz)
    3 - buck isns out   (off)
    4 - buck vsns out  (4khz)
    9 - ISNS (25 khz)
    12 -pot 2 (25khz)
    13 -buck isns in (off)
    14 -buck isns in  (4khz)

    For this experiment I've set AN3 and AN13 trigger source to none.  POTs are adjustable which make things more clear.  The control loop is 25khz, 1/4 the PWM freq, and many ADCs are sampled at 25khz, however there is a round robin scan list with 6 items (including 4 and 14) - one of which is scanned on each 25khz control cycle.  So AN4 is sampled every 240uS, as is AN14 - but 40uS later.  In the scope trace, 2 (cyan) is AN4 and 1 (yel) is AN14
    The first capture, both POTs are set to ~0V.  In the second capture POT1 is set to 3.3V, POT2 is unchanged.
    I also observed that as the POT is turned the voltage blip smoothly changes

    The DC voltage of the AN4 and AN14 is about 1.15V.  The delta V that occurs when the ADC sample occurs is ~ -50mV or +100mV. 

    If we assume that Chold isn't discharged, and that Chold is the voltage of the POT, then delta V should allow one to calculate Chold.  Based on this, and my crude delta V estimates, Chold is 390pF/23 or 390/21.5 or around 17pF.   Obviously a lot larger than the model states.  Of course the model also states that Chold is discharged between samples.
     
    Also failed to mention my sample and hold time.  My ADC clock is 70 Mhz, and for these scope captures sample time was 50 clocks or 700nS.  Typically I run SH of 10 clocks - but was experiment with the value to see if it had an effect - it doesn't. 
     
     

    Attached Image(s)

    #5
    cbarn
    Starting Member
    • Total Posts : 50
    • Reward points : 0
    • Joined: 2007/01/20 11:02:14
    • Location: 0
    • Status: offline
    Re: dspic33CK - ADC channel coupling behavior 2019/01/28 07:00:32 (permalink)
    0
    cobusve
    How are you fully discharging CHold? You would have to leave CHold connected to Vss for long enough to accomplish this, perhaps you are not meeting the time requirement?
    If there remains a voltage on CHold from the prior conversion it would cause exactly what you are describing ...



    The 12bit ADC section (7005213f) has the analog input model.  This document is referenced from the 33CK family datasheet.    However given what I'm seeing, I suspect the input model isn't accurate for the C devices.  The descriptions are for a 33C device (not 33FJ) - but I that analog input seems like I recall for 33FJ....

    Attached Image(s)

    #6
    du00000001
    Just Some Member
    • Total Posts : 2549
    • Reward points : 0
    • Joined: 2016/05/03 13:52:42
    • Location: Germany
    • Status: offline
    Re: dspic33CK - ADC channel coupling behavior 2019/01/28 08:48:15 (permalink)
    0
    You should start with DC-coupling the channels!
    Do I interpret the plots correctly when assuming 50 µs/DIV?
     
    And you ignore the statement in the DS section about the source resistance being <= 5 KOhms. This is NOT about "AC resistance" - this is about plain DC resistance!
    (Although one could cope with the voltage drop during charging CHold arithmetically.)
     
    And a reasonable value for some "buffer" capacitance is more like 1 nF and beyond (10 nF might be fine) - not 390 fancy pF !
     

    PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)
    #7
    cbarn
    Starting Member
    • Total Posts : 50
    • Reward points : 0
    • Joined: 2007/01/20 11:02:14
    • Location: 0
    • Status: offline
    Re: dspic33CK - ADC channel coupling behavior 2019/01/28 09:27:51 (permalink)
    0
    What do you mean - "DC coupling the channels"?
    Yes 50uS / div.  Didn't ignore the statement - I think its only about Cpin - which is a 1 or a few pF.  Cpin is in parallel with the 390. 
     
    But the question is - is Chold being discharged between samples?  Is it supposed to be?
     
    #8
    Jim Nickerson
    User 452
    • Total Posts : 5842
    • Reward points : 0
    • Joined: 2003/11/07 12:35:10
    • Location: San Diego, CA
    • Status: offline
    Re: dspic33CK - ADC channel coupling behavior 2019/01/28 09:32:09 (permalink)
    0
    cbarn
    But the question is - is Chold being discharged between samples?  Is it supposed to be?

    How do you determine Chold is not discharged ?
    How do you imagine the ADC sampling might work if Chold was not discharged ?
     
    #9
    du00000001
    Just Some Member
    • Total Posts : 2549
    • Reward points : 0
    • Joined: 2016/05/03 13:52:42
    • Location: Germany
    • Status: offline
    Re: dspic33CK - ADC channel coupling behavior 2019/01/28 09:41:44 (permalink)
    0
    The 5 kOhms is not about CPin (which is more a nuissance than helpful), it's about the SOURCE RESISTANCE - the resistance of YOUR source!
    And from the voltage curve I can tell that your time constant of 17.5 µs somewhat holds - as it takes about 50 µs to replenish the charge "drawn" by CHold.

    PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)
    #10
    cbarn
    Starting Member
    • Total Posts : 50
    • Reward points : 0
    • Joined: 2007/01/20 11:02:14
    • Location: 0
    • Status: offline
    Re: dspic33CK - ADC channel coupling behavior 2019/01/28 11:40:27 (permalink)
    0
    "Note 1: The CPIN value depends on the device package and is not tested. The effect of the
    CPIN is negligible if Rs <= 5 k."
     
    Are we talking about Note 1?    Okay so Cpin isn't negligible in my application - I didn't neglect it.  Cpin is in parallel with 390pF and thus adds to it.
    #11
    cbarn
    Starting Member
    • Total Posts : 50
    • Reward points : 0
    • Joined: 2007/01/20 11:02:14
    • Location: 0
    • Status: offline
    Re: dspic33CK - ADC channel coupling behavior 2019/01/28 11:53:25 (permalink)
    0
    JANickerson
    cbarn
    But the question is - is Chold being discharged between samples?  Is it supposed to be?

    How do you determine Chold is not discharged ?
    How do you imagine the ADC sampling might work if Chold was not discharged ?
     



    The question started with a guess last night - but with the new data I've collected - I have my answer.

    If Chold is not discharged and we assume it has the voltage of the previous channel (Vprev), and the Hi DC R channels is V0 then the expected deltaV is (on a time scale that current flow via the resistors is ignored.)
    q_Chold = Chold * (Vprev-V0)    // change in charge on Chold
    deltaV = q_Chold/390pF

    If Chold is discharged (0 volts) then :
    q_Chold = Chold * V0   // change in chage on Chold to get it to V0
    deltaV  = Chold/390pF * V0
    The blips in the voltage in the scope traces are what I call deltaV - but Chold would need to be about 16pF to explain the delta V. 
    So I claim there are 2 issues:
    1) Chold isn't discharged as stated in the DS
    2) Chold isn't ~5 pF as stated in the DS.

    In anycase, there is definarly cross coupling as the voltage on the previous sampled channels effects the deltaV of my high DC impedance circuit.

    Have I missed something?
    #12
    Jim Nickerson
    User 452
    • Total Posts : 5842
    • Reward points : 0
    • Joined: 2003/11/07 12:35:10
    • Location: San Diego, CA
    • Status: offline
    Re: dspic33CK - ADC channel coupling behavior 2019/01/28 12:09:24 (permalink)
    0
    Have all your measurements been made at the same adc sample rate ?
    Do they change if the adc sample rate is lowered ?
    edit: add adc
    post edited by Jim Nickerson - 2019/01/28 12:10:55
    #13
    du00000001
    Just Some Member
    • Total Posts : 2549
    • Reward points : 0
    • Joined: 2016/05/03 13:52:42
    • Location: Germany
    • Status: offline
    Re: dspic33CK - ADC channel coupling behavior 2019/01/28 12:15:55 (permalink)
    0
    cbarn...    Okay so Cpin isn't negligible in my application -   ...

    !!! OMG !!! What an ignorant!  mad
    I p.. on your capacitance (too small to be significant) - it's the source (series) resistance that counts!
    I won't repeat this another time.
     
    What I repeat: What is your source resistance ?
     
    Your curves are clearly showing voltage transistions during sampling (recovery takes 50 µs) - the result of a too-high source resistance. Does this - ever-so-slowly - settle now?

    PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)
    #14
    cbarn
    Starting Member
    • Total Posts : 50
    • Reward points : 0
    • Joined: 2007/01/20 11:02:14
    • Location: 0
    • Status: offline
    Re: dspic33CK - ADC channel coupling behavior 2019/01/28 14:13:19 (permalink)
    0
    all done here.

    post edited by cbarn - 2019/01/29 06:05:12
    #15
    T Yorky
    Super (Thick) Member
    • Total Posts : 514
    • Reward points : 0
    • Joined: 2012/08/28 02:07:35
    • Location: UK
    • Status: offline
    Re: dspic33CK - ADC channel coupling behavior 2019/01/30 11:22:21 (permalink)
    0
    @ du00000001,
    'You can lead a horse to water, but you can't make him drink'
    #16
    cbarn
    Starting Member
    • Total Posts : 50
    • Reward points : 0
    • Joined: 2007/01/20 11:02:14
    • Location: 0
    • Status: offline
    Re: dspic33CK - ADC channel coupling behavior 2019/03/18 16:59:44 (permalink)
    0
    A few weeks ago Microchip got back to me with a useful answer:

    "In new devices the SAR core was updated, however, there were some details not correctly reflected in the data sheet. The Chold capacitor is 2.4pF (see “input_circuit.png” in attachment). This capacitor is NOT discharged after the end of conversion. To avoid a cross coupling, the sampling time should be big enough. However, it may not be possible to achieve if one channel in the scan list has a high impedance source and requires additional sampling time.

    We have made note of the need for this documentation to be corrected, but hopefully that answers your question for now. If you have any further questions, just let me know, and I will get back to you as soon as I can. Otherwise, feel free to close the case."
    -----------------
     
    "My colleague hadn't gotten around to the issue, sorry, but we are very busy here now.
    This morning he was able to verify your calculation, the Chold is coming out to be 18.6 pF.
    With that information, my colleague is working with the design team to further clarify the operational behavior."


    post edited by cbarn - 2019/03/26 15:23:45
    #17
    JPortici
    Super Member
    • Total Posts : 623
    • Reward points : 0
    • Joined: 2012/11/17 06:27:45
    • Location: Grappaland
    • Status: offline
    Re: dspic33CK - ADC channel coupling behavior 2019/04/16 08:05:52 (permalink)
    0
    I want also to confirm the issue.. I too was getting coupling noise between adjacent channels (ADC channels, not pins. for example AN8 (pin 43) would disturb AN9 (pin 20) and so on)
     
    In my case the MCU is acquiring a number of Analog channels through the shared core. Single acquisition sample rate is 128kS/s (243TAD sampling + 14.5 TAD conversion -> TAD 31.25ns or 1/32MHz)
    The system samplerate is limited to 10KS/s per channel, as the conversion sequence is initiated by a 10kHz pulse from REFO module, routed through the ADC trigger using CLC1. At the begin of each acquisition there is a 10kHz pulse, the envelope follows the shape of the signal at the previous AN channel
     
    In my case i have only one "high" impedance source (switched resistor array, to read a dipswitch with an analog channel) but it is bypassed at the ANx pin and that is the only channel that doesn't show coupling
     
    The other channels are instead a filter + attenuator that goes into a final buffer made with a MCP600x. a 220R resistor from OPA output to ANx pin (Also changed with 100R but that didn't change the shape or the duration of the noise erroneous pulse.
     
    Obligatory scope shot

     
    CH1: Input, 0-5V Sine
    CH2: Output (in this test i am acquiring and recreating the signal with a PWM channel to test gain and ripple errors)
    CH3: ADC Input, before and after the resistor (Again, 220R or 100R or even a short won't change the pulse shape. Pulse was acquired with proper probing) so the pulse is at the output of the MCP600x buffer, but is not at the + input, as it's too fast to propagate along the slow MCP. the previous AN channel was grounded so you see the pulses that tends to go to gnd.
     
    While i'm writing this i'm wondering if a faster OPAMP would be able to eliminate the pulse.. It's not required by the application but it's still annoying to see.
     
     

    Attached Image(s)

    #18
    Howard Long
    Super Member
    • Total Posts : 638
    • Reward points : 0
    • Joined: 2005/04/04 08:50:32
    • Status: offline
    Re: dspic33CK - ADC channel coupling behavior 2019/04/16 08:42:15 (permalink)
    0
    I am not sure of the bandwidth requirements of the input other than Nyquist limitation due to your 10kHz sample rate, but your scope shot seems to show ~20Hz sine wave. Can you do something relatively simple and add, say, a 100R resistor to the opamp output for isolation, plus, say, a 100nF tank cap on the ADC pin? 
    #19
    du00000001
    Just Some Member
    • Total Posts : 2549
    • Reward points : 0
    • Joined: 2016/05/03 13:52:42
    • Location: Germany
    • Status: offline
    Re: dspic33CK - ADC channel coupling behavior 2019/04/16 08:48:39 (permalink)
    5 (1)
    @JPortici
    1 MHz GBW for the MCP600x is not really much.
     
    Once again I'm referring to a competitor:
    TI (namely Bonnie Baker) has published a lot on analog circuits - including the buffering of ADC inputs. (Sorry - currently none of her publications at hand.)
    One of the issues is buffer bandwidth, another one the buffer's drive strength. The slew rate might be an indication for the drive strength, and 0.6 V/µs is way from 1 MHz GBW for more than (really) "small signal bandwidth".
     
    Basically you have to charge the ADC's sampling cap - preferably without any effect on the input. (Which is next to impossible.)
    Thus, a faster OpAmp with a significantly higher slew rate (I'd recommend something equal or beyond 5 V/µs) is expected to yield better results.
    You've already implemented the cheapest way to improve the signal: adding a reasonable capacitor (2- to 3-digit nFs should be a viable approach). Unless this capacitor does slow-down your input too much, this should be feasible.
    (And pay attention if you have a buffer driving the input/buffer cap: not all OpAmps/buffers accept such high capacitive loads! Some answer such capacitive loading with excessive oscillations.)
     
    P.S.:
    6 .. 23 mA short circuit current (depending on the supply) is poor. Look for a "non-low-power" buffer or OpAmp: drive strength is associated to quiescent current: low quiescent current => low(er) drive strength.
    post edited by du00000001 - 2019/04/16 08:51:08

    PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)
    #20
    Page: 12 > Showing page 1 of 2
    Jump to:
    © 2019 APG vNext Commercial Version 4.5