Hot!32MX795F512L Timer 4/5 32 bit interrupt unstable

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Spottymaldoon
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2019/01/15 11:59:27 (permalink)
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32MX795F512L Timer 4/5 32 bit interrupt unstable

I'm setting up an interrupt using T4 and T5 configured as 32 bit. Right now I only need this one interrupt so I am setting priority and sub-priorities at 1.
 
I understand that, in 32 bit timer mode, the EVEN number register i.e. T4 becomes 32 bit by adding the odd register T5 so that putting TMR4=0x0 also clears TMR5 and similarly PR4  then requires a 32 bit setting.
Setup is like this:

TMR4=0x0;//clear registers
TMR5=0x0;
T4CON=0x0078;//T4/5 timers in 32 bit mode and 1/256 divider
PR4=0x0000FFFF;//for the test around .4 sec

 
Now when it comes to doing timed interrupt using 32 bit T4/5 I understand that this needs to be done referencing only T5, not T4 so that we set the T5IE and clear the T5IF which I find confusing. But, anyway:
 

IPC5SET = 0x00000005; //priorities 1 and sub 1

Then in main() which has been working fine until now I trigger a repeating interrupt:

while(1)
{
_LATD9=!_RD9;//to make the RD9 connected LED flash with alternate interrupts
TMR4=0; //just to be sure
IFS0CLR = 0x00100000; // Clear the Timer5 interrupt status flag -just to be sure
IEC0SET = 0x00100000; // Enable Timer5 interrupts
T4CONSET = 0x8000; // Start timer
while(!IFS0bits.T5IF); //wait for flag to go up
}

To add to the confusion, in the 32MX family manual  Section 14, the example given formats the ISR as:
void __ISR(_Timer_1_Vector,ipl3)Timer1Handler(void)
which argument doesn't compile because it should be upper case:
void __ISR(_TIMER_5_VECTOR, ipl1) _Timer5Handler(void)   (using my settings) -
So my ISR is:

void __ISR(_TIMER_5_VECTOR, ipl1) _Timer5Handler(void)  
{
IFS0CLR = 0x00100000; // Clear the Timer5 interrupt status flag
T4CONSET = 0x0000; // Stop timer
TMR4=0x0; //clear timer
}//end ISR

 
What I sometimes get is an LED which flashes as I wanted - but after around 10 cycles it freezes and other times it just freezes with no flash. The setup is unstable - advice please!
 
PS Sorry, I messed up the format - fixed now
post edited by Spottymaldoon - 2019/01/15 12:08:30
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    cvm
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    Re: 32MX795F512L Timer 4/5 32 bit interrupt unstable 2019/01/15 15:33:00 (permalink)
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    I'm not sure you can be polling that flag when it is cleared in the isr. I'm also not sure why you are using the port bit (_RD9) instead of the LAT bit to toggle- maybe unimportant, but it can be depending on what that port/pin is actually doing.
     
    Here is my simple test on a pic32mm with the same type of timer-

    #include <cstdint>
    #include "Pins.hpp"
    #include "Osc.hpp"
    #include "Irq.hpp"
    #include "Timer23.hpp"
    Timer23 t2{ Timer23::TMR2 };
    Pins ledB{ Pins::C15, Pins::OUT};
    int main()
    {
    //set osc to 24MHz
    Osc osc;
    osc.pll_set(osc.MUL12, osc.DIV4);//8*12/4 = 24MHz
    Irq::init( Irq::TIMER_3, 1, 0, true );
    Irq::global( true );
    t2.mode32( true);
    t2.period( 12000000 ); //24Mhz/2, 1Hz
    t2.on( true );
    for(;;){
    osc.idle();
    }
    }
     
    ISRautoflag( TIMER_3 ){
    ledB.invert();
    }}//<-yes, 2 of them
    I get the blue led flashing at 1Hz.
    #2
    qhb
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    Re: 32MX795F512L Timer 4/5 32 bit interrupt unstable 2019/01/15 15:37:57 (permalink)
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    cvm
    I'm not sure you can be polling that flag when it is cleared in the isr.
    I'm also not sure why you are using the port bit (_RD9) instead of the LAT bit to toggle- maybe unimportant, but it can be depending on what that port/pin is actually doing.

    Both are very valid points. The former means it's unlikely the LED will ever flash.
     
    #3
    Spottymaldoon
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    Re: 32MX795F512L Timer 4/5 32 bit interrupt unstable 2019/01/16 09:59:47 (permalink)
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    Thanks cvm and qhb - now you mention it, in very clear English, your point seems obvious and I've made the necessary corrections but, so far, nothing happens.I shall keep on it.
     
    cvm, which compiler platform are you using in your example please?
     
    I'm taking for granted that once T4CON has been set in 32 bit mode, registers like TMR4 and PR4 become 32 bit by combining with T5.
    And also that the  associated interrupt register bits are then IF0bits.T5IF and IE0bits.T5IE  i.e not T4IF and T4IE as seems intuitive to me.
     
    #4
    cvm
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    Re: 32MX795F512L Timer 4/5 32 bit interrupt unstable 2019/01/16 11:08:36 (permalink)
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    cvm, which compiler platform are you using in your example please?
    XC32 c++. I have a recent post where I explain my use of c++.
     
    I'm taking for granted that once T4CON has been set in 32 bit mode, registers like TMR4 and PR4 become 32 bit by combining with T5.
    Although I must have figured it out when I wrote my 'drivers' (since I return a uint32_t- which in the 16bit mode is harmless), I started to doubt what was happening, so ran some tests with the debugger. When the T32 bit is enabled, the lower timer acts as 32bits- both the timer and the PR. The upper timer flag is the one that gets set on match, and the lower flag does not change. On a pic32mm at least, and I would be surprised if the same type of timer is different on an mx.
     
    I have not tested, but suspect you can also write to the upper timer and its pr (in 32bit mode) and the result would be a change of the upper 16bits of the lower timer.
    post edited by cvm - 2019/01/16 11:12:46
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    Larry.Standage
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    Re: 32MX795F512L Timer 4/5 32 bit interrupt unstable 2019/01/16 11:56:08 (permalink)
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    A few notes about your code:
    T4CONSET = 0x0000; // Stop timer
    does nothing. If you wanted to stop the timer, try
    T4CONCLR = 0x8000;

    Your setup of the timer is fine, but how you tell the main code to go ahead and blink the LED needs to be done with a flag in your code. For example, a volatile unsigned int that can be set by the ISR. When the main code sees that the flag is set, it toggles the LED and clears that flag.
    In other words, the ISR should handle the peripheral (Timer and Interrupt flags), and let the main code only do what is required.
    I created a version of your code that seems to work for me. It's running, and I don't see any issues with the blink. Try it out, and let me know if it helps you understand what is going on.
    #6
    NorthGuy
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    Re: 32MX795F512L Timer 4/5 32 bit interrupt unstable 2019/01/16 12:11:34 (permalink)
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    There's no reason to use a 32-bit timer if PR is less than 0x10000. I wouldn't expect this to work. Try PR above 0x10000.
    #7
    davekw7x
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    Re: 32MX795F512L Timer 4/5 32 bit interrupt unstable 2019/01/16 12:42:27 (permalink)
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    Spottymaldoon

    ...

    I'm taking for granted that once T4CON has been set in 32 bit mode, registers like TMR4 and PR4 become 32 bit by combining with T5.



    That's correct.

    Spottymaldoon

    And also that the  associated interrupt register bits are then IF0bits.T5IF and IE0bits.T5IE  i.e not T4IF and T4IE as seems intuitive to me.



    Well, intuition or not, the fact is that the 32-bit counter consists of TMR5:TMR4 with TMR5 being the most significant 16 bits, so T5IF indicates 32-bit timer overflow.


    My suggestion: Get the 32-bit stuff working as you expect, without interrupts.  Then do whatever you need to do with interrupts in order to meet the needs of your application.

    Give it a long enough period that it can't be done with a 16-bit timer, and make the timer toggle an LED at a rate that can be visually validated.

    The code snippet that I have attached toggles an LED every second, using a system frequency of 80 MHz and a period register setting of 79999999.  PIC32MXF512L, XC32 version 2.10 (Free Mode) Optimization level 1
     
    Output:
    Compiled on Jan 16 2019 at 11:06:55 by XC32 version 2100
    PR4 = 79999999 = 0x04C4B3FF
             1
             2
             3
             4
             .

             .



    Once you are sure that that the timer stuff is working, then go back to your interrupt stuff and do whatever is required to meet your project's requirements.


     
    Regards,

    Dave
    post edited by davekw7x - 2019/01/16 13:33:31

    Sometimes I just can't help myself...
    #8
    cvm
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    Re: 32MX795F512L Timer 4/5 32 bit interrupt unstable 2019/01/16 13:41:55 (permalink)
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    if PR is less than 0x10000. I wouldn't expect this to work

    Give it a long enough period that it can't be done with a 16-bit timer

    PR works fine from 1-0xFFFFFFFF in 32bit mode.
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    Spottymaldoon
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    Re: 32MX795F512L Timer 4/5 32 bit interrupt unstable 2019/01/17 08:21:46 (permalink)
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    CVM - thanks for your further input and elucidation of the 32 bit timer hierarchy. Earlier I'd written to PR4 and PR5 separately in 32 bit mode and that worked fine - the 32 bit write only to PR4 was just more elegant.
    Larry.Standage - That was a dumb slip of mine and thanks for pointing it out. I am really grateful to you for taking the trouble to test the code and I am sure I shall now get the thing going today. It always seems to take more than one silly mistake to cause a problem (software or hardware). I have not seen the macro  __builtin_enable_interrupts() (which doesn't compile on C32) and although it is mentioned in the CX32 manual, there's no explanation other than it enables global interrupts.
    I am autodidact in software (did Fortran with punch-cards in the sixties but nothing till I retired 20 years back) so working up to PIC32 from 16F has been a challenge but a lot of fun.
    NorthGuy - thanks for the input. This was just a test to have the thing flash at around 1Hz - I need a muti-minute timer in my application.
    Davekw7x - I'm touched that you guys are taking trouble to respond to my problem. Thanks to all your inputs I should have everything sorted today as I have (a while back) done a 32 bit timer on the 24FJ and all of your inputs are much appreciated. Believe it of not I'm still using MPLAB8 along with C32 and have, to date, found MPLABX somewhat daunting.
     
    post edited by Spottymaldoon - 2019/01/17 08:23:17
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    Spottymaldoon
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    Re: 32MX795F512L Timer 4/5 32 bit interrupt unstable 2019/01/17 16:09:50 (permalink)
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    A follow-up question since the 32 bit timer is working fine but not with interrupt.
    Which registers are involved in the CX32 macro  __builtin_enable_interrupts() ?
    I don't have this in C32 and can't see any requirement for a global interrupt enable (GIE) for this chip in the Family Reference Manual.
     
    void INTEnableInterrupts(void) compiles but so far nothing happening!
    post edited by Spottymaldoon - 2019/01/17 21:15:04
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    davekw7x
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    Re: 32MX795F512L Timer 4/5 32 bit interrupt unstable 2019/01/17 21:34:01 (permalink)
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    Spottymaldoon
    ...
    Which registers are involved in the CX32 macro  __builtin_enable_interrupts() ?
    ...

     
    Sets the IE bit in the CP0 (Coprocessor 0) register 12, the Status register, by executing the asm instruction "ei"
    (In Section 2 of the Family Reference manual, description of the Status register starts on page 2-26 of DS61113E)
     
    Before I discovered __builtin_enable_interrupts(), I just put in the in-line assembly statement asm("ei"); which I had found in numerous PIC32 code examples.  I think use of builtin functions is more elegant.
     
    Note that, as indicated in the post from Larry Standage, before enabling interrupts, you should set MVEC (in INTCON) to 1 (multi-vectored interrupt mode).
     
    Generally speaking, my initialization sequence might look like this:
    void init_system(void)
    {
        INTCONSET = _INTCON_MVEC_MASK;
        
        init_io();
        init_timers();
        init_uart2();

        // Initialize other stuff
        
        __builtin_enable_interrupts();
    } // End of init_system()

     
    Regards,

    Dave
    post edited by davekw7x - 2019/01/17 22:08:20

    Sometimes I just can't help myself...
    #12
    Spottymaldoon
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    Re: 32MX795F512L Timer 4/5 32 bit interrupt unstable 2019/01/18 09:07:08 (permalink)
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    Very many thanks, Dave - I'm in business now - you have been very helpful.
     
    In C30 I found that the equivalence to CX30's  __builtin_enable_interrupts(); is your asm("ei"); or INTEnableInterrupts(); (32 bit Peripheral Library Guide, Section 7.1). Thanks also for the explanation.
     
    What a relief!
    #13
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