Hot!PIC32MZ DA with internal DDR2 RAM - unexpected write speed

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marekb
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2019/01/06 16:26:11 (permalink)
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PIC32MZ DA with internal DDR2 RAM - unexpected write speed

Hello,
I got unexpected mem write speed results durning testing internal ddr2 ram on PIC32MZ2064DAH169.
After ddr2 initialization I use memset() call with the address argument set to cacheable segment:
tmr=ReadCoreTimer();
memset((void *)0x88000000,0xAA,32000000);
tmre=ReadCoreTimer();
printf("done in %ums\r\n",(tmre-tmr)/MS_TICK);

 
it takes 885ms to fiilup 32M bytes array (200MHz clock). When address is set to 0xA8000000 (uncacheable segment) it takes only 204ms. Why write to cacheable segment is 4x slower?
#1

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    andersm
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    Re: PIC32MZ DA with internal DDR2 RAM - unexpected write speed 2019/01/06 16:35:44 (permalink)
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    What happens if you configure the cache to write-back instead of write-through?
     
    Edit: Walking through memory like that is going to incur a ton of cache misses, which come with a performance penalty.
    post edited by andersm - 2019/01/06 21:57:40
    #2
    crosland
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    Re: PIC32MZ DA with internal DDR2 RAM - unexpected write speed 2019/01/07 01:51:29 (permalink)
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    You are writing way more data than fits in the cache so you will be continually hitting dirty cache lines.
     
    Is the memset lib fn optimised at all?
     
    This is not a meaningful test of cache performance.
    #3
    marekb
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    Re: PIC32MZ DA with internal DDR2 RAM - unexpected write speed 2019/01/07 03:49:00 (permalink)
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    Things get stranger when I replace address argument with a poniter:
    char *mem=0x88000000;
    tmr=ReadCoreTimer();
    memset((void *)mem,0xAA,32000000);
    tmre=ReadCoreTimer();
    printf("done in %ums\r\n",(tmre-tmr)/MS_TICK);

     
    It desn't matter where points mem (0x88000000 or 0xA8000000). In both cases it takes 204ms.
    How explain this?
     
    #4
    NorthGuy
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    Re: PIC32MZ DA with internal DDR2 RAM - unexpected write speed 2019/01/07 11:21:53 (permalink)
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    You need to post disassemblies of these. If you get different timing with all other settings being equal, there must be differences.
     
    204 ms is still slow - 156 MBytes/sec compared to 800 MBytes/sec memory bandwidth. Your writes are not limited by memory, but by CPU - if it is at 200 MHz, then, in your experiment, it takes about 5 instruction cycles to write a single 32-bit word - this uses only about 20% of the memory max bandwidth.
     
    #5
    marekb
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    Re: PIC32MZ DA with internal DDR2 RAM - unexpected write speed 2019/01/07 15:23:41 (permalink)
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    But AFAIK memset use byte-by-byte transfer not 32 bit words, it must be slower than 32bit word copy/move.
    Forget about no differ when pointer is used with memset, it was my mistake. Anyway it acts the same, faster if accessed 0xA8000000, slower if 0x88000000.
    #6
    andersm
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    Re: PIC32MZ DA with internal DDR2 RAM - unexpected write speed 2019/01/07 15:50:58 (permalink)
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    Depends on the compiler and C library. It is very common to optimize memset to use wider writes when possible. I still suspect cache misses, you could try using the performance counters to measure stall cycles (the microAptiv core unfortunately doesn't have the detailed cache counters of its "big brother" interAptiv).
    #7
    Mark Roush
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    Re: PIC32MZ DA with internal DDR2 RAM - unexpected write speed 2019/01/10 20:58:56 (permalink)
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    Just a guess.  Cache is really meant to speed up reads.  When you write, not only the cache is written to, also the actual physical memory must also be written to so they are kept in sync.
    #8
    crosland
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    Re: PIC32MZ DA with internal DDR2 RAM - unexpected write speed 2019/01/11 02:12:45 (permalink)
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    Mark Roush
    Just a guess.  Cache is really meant to speed up reads.  When you write, not only the cache is written to, also the actual physical memory must also be written to so they are kept in sync.



    If the memory being written is not already in cache (very likely with the OPs test method) then the memory has to first be read to bring a line into the cache, then the new write data can be merged into the cache line. It may be written immediately or only when that cache line is required for a different memory address.
     
    The OP has not responded at all to posts #2 or #3.
    #9
    friesen
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    Re: PIC32MZ DA with internal DDR2 RAM - unexpected write speed 2019/01/11 06:03:26 (permalink)
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    I have noticed the long time it takes similar to the OP. Ideally non cache space would get memset, and then clean the cache, but can that get done without iterating over the complete address space?

    Erik Friesen
    #10
    andersm
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    Re: PIC32MZ DA with internal DDR2 RAM - unexpected write speed 2019/01/11 09:05:35 (permalink)
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    friesenIdeally non cache space would get memset, and then clean the cache, but can that get done without iterating over the complete address space?

    Yes, you can invalidate all or parts of the cache. See AN1600, and section 50 of the FRM, or the MIPS architecture manuals for details on using the "cache" instruction. Harmony's devcon library has some functions for managing the cache.
    #11
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