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H2.06: SPI Interrupt Mode Clarification

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ABaum89
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2018/12/23 10:33:23 (permalink)
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H2.06: SPI Interrupt Mode Clarification

I am currently writing an application which communicates with the LTC1856 ADC and I'm curious about some of the finer points of SPI Interrupts concerning the Harmony framework.
 
When "Interrupt Mode" is selected in the MPLAB Harmony Configurator, interrupt priority selection is provided.  The chip that I'm using necessitates a simultaneous write/read, therefore I would expect that both TX and RX occur at the same time.  How is this handled with interrupts?  Why would I need two interrupts for the same operation? 
 
From the Harmony Reference, Volume V, I gathered that enabling interrupt mode simply ensures that the Task function is called immediately rather than handled in the main while(1) loop.  To me, this means that I would expect one interrupt, while in the picture attached, I see three (Tx,Rx,Err).

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LostInSpace
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Re: H2.06: SPI Interrupt Mode Clarification 2019/01/06 13:35:25 (permalink)
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In general - for SPI the write bits out to MOSI happens with the same clock as the read bits into MISO. There is no interrupt involved between the MOSI and MISO portion.
 
The interrupt comes into play when you say write, then go off to other things, then the write completes and you get an interrupt saying that the write is complete.
 
That's how I understand it...
 
 
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qhb
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Re: H2.06: SPI Interrupt Mode Clarification 2019/01/06 14:50:33 (permalink)
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Of course, things get a bit more complicated when you have FIFO buffers on the write and read.
The OP has not mentioned which PIC part they are using.
 

Nearly there...
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