Hot!PIC32MZ DA FRC with DDR

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cjohnson
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2018/10/18 09:45:27 (permalink)
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PIC32MZ DA FRC with DDR

Just got in my prototypes with a PIC32MZ2064DAG176 chip, ethernet, spi memory, rtc module and spkr.
 
Made the mistake of looking over the POSC can't accept crystal operation errata and built the board the handle an HS 24 MHz crystal.
 
Is there anyway to run the DDR MPLL (Memory PLL) off of the FRC or am I stuck modifying these board to use an EC? I can almost get full startup on the FRC, but the DDR wont initialize because its clock input is missing. 
post edited by cjohnson - 2018/10/18 09:47:13
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    Wavelength
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    Re: PIC32MZ DA FRC with DDR 2018/10/19 06:50:28 (permalink)
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    CJ,
     
    I think you have to modify something. Especially if you want to use Ethernet or USB as those both require a more stable clock than the FRC can give you.
     
    If you only wanted to test the damn DDR,  you could probably generate from the FRC a ~24MHZ clock (on a REFCLKx output) and remove the crystal stuff you have now and wire the output of the REFCLKx to the pad of the crystal at OSC1.
     
    Unlike the requirements for Ethernet and USB the DDR probably does not require as much precision as those peripherals do.
     
    Thanks,
    Gordon
    #2
    cjohnson
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    Re: PIC32MZ DA FRC with DDR 2018/10/19 07:54:39 (permalink)
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    Wavelength,
     
    So I've got a 50 MHz oscillator for the ethernet, a 32.768 for an external RTCC (again the eratta), and a 24 MHz oscillator for the PIC32. 
     
    It's really weird why the FRC is not routed in to the DDR in anyway. I'll add a wrapping wire from a REFCLK output to the input of OSC1 and remove the rest of the 24MHz clock.
     
    I'll get back to you when I've tried it out.
     
    Looking back I wish I would have chose an STM part for this. Their product's erattas don't have half the issues these PIC32MZ products have. I dont understand how Microchip gets away with false advertising on their product pages tbh. Unfortunately (or fortunately, however you look at it) I have almost finished the code for this project and would take a lot of time to redo the project.
     
    Thanks,
     
    Colby
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    Wavelength
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    Re: PIC32MZ DA FRC with DDR 2018/10/19 08:41:27 (permalink)
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    Colby,
     
    I am sure there are reasons why they push the the FRC to things that really should not be there and why they didn't on the DDR.
     
    Do note that there are always combinations of things with the MZ that don't work very well. Analog effects this which effects that and then your stuck. I spent 8 months on an MZ product that had to be canned.
     
    May I ask what you are trying to do?
    Thanks,
    Gordon
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    cjohnson
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    Re: PIC32MZ DA FRC with DDR 2018/10/19 08:55:06 (permalink)
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    Wavelength,
     
    This has been a long project...we originally designed this on a PIC32MX and the project got canned. Now the project is live again, due to the market it is in and the changes that are coming with 5G...
     
    Its a custom board with ethernet (hosted web server, snmp and eventually remote update), spi memory, 7 inch touch screen, rtc, and a couple other things. It's an industrial controller that talks to other boards we developed that basically are take commands dont ask questions boards.
     
    It's got to be low cost, so all oscillator clocks were removed in favor of the much cheaper crystals. That's kind of the high level picture. There's obviously a lot more to it, but that's as in depth as i can go.
     
    Currently all of the graphics, majority of the control logic, etc are done. The company we are building this for is looking to show it off later this year.
     
    Thanks,
     
    Colby
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    Wavelength
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    Re: PIC32MZ DA FRC with DDR 2018/10/19 09:19:29 (permalink)
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    Colby,
     
    You should be fine with that type of design. Oscillators are pretty cheap now, you maybe able to fit available ones on the pads you have for the crystal and then wire in the 3V3 power.
     
    You know that really the 24/48 EC is really for the USB controller HS to generate the correct lock frequencies required for HS.
     
    You could use a 74LVC1G80 or a 74LVC1G74 as a clock divider from the 50Mhz Ethernet clock (some phy's have a 25Mhz output as well as the 50Mhz) so your input frequency to the OSC1 is 25Mhz, tie DATA to Q- and 50MHZ->Clk and it creates a good divider. Then just set the PLLIDIV, PLLMULT and PLLODIV correctly to get ~correct frequency. I don't thing the DDR stuff needs to be exact, they probably just want a really stable clock frequency.
     
    Thanks,
    Gordon
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    cjohnson
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    Re: PIC32MZ DA FRC with DDR 2018/10/19 11:37:44 (permalink)
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    Gordon,
     
    Trying to get it working on minimal complication, so if I can't get the FRC to work as it is right now with the REFCLK1O I'll make it work with a oscillator clock like I had before.
     
    So I've got the bits in Harmony set so that it generates a clock on pin 8. Testing the output with the DDR initialization commented out I can see the clock does in fact work. 
     
    That's the good news.
     
    DDR initialization takes place before the IO output clock is activated, and this is where the problem starts. I moved the DDR clock initialization to a separate function that occurs after the SYS_CLK_Initialization is called, but when I get to the DDR initialization there is still no clock present with pin 8 wired to the OSC1I.
     
    How should I have the clock diagram setup? Do I set it up as EC? I'm not sure, I've tried it as HS and EC but still can't get a clock signal in when I hit the DDR Initialization.
     
    Any ideas?
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    cjohnson
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    Re: PIC32MZ DA FRC with DDR 2018/10/19 12:06:32 (permalink)
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    Update:
     
    Moved the DDR Initialize function below the DEVCON initialization and I'm able to get a clock signal in to the MPLL. Now getting hung up on the SYS_MEMORY_Initialize() funciton. Going to try reducting the MPLL clock configuration down to like 10 MHz to see if that fixes it.
     
    Will update soon.
     
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    Wavelength
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    Re: PIC32MZ DA FRC with DDR 2018/10/19 12:16:46 (permalink)
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    Colby,
     
    Should be set to EC, now since you have not clock at boot time this could cause a problem and then you might have to set this up after. I am not a big fan of Harmony so I am not sure how you would do that. But if you hard code it you would set the syskeys to unlock the coprocessor then set the the new oscillator and other stuff like the pll and stuff for the DDR and everything else. This would have to be done after you have a clock out of REFCLKO.
    Also would make sure the TRIS is setup for OSC1 and REFCLKO pins. You can pretty much set all this stuff up before it happens.

        SYSKEY = 0xAA996655; // unlock 1
        SYSKEY = 0x556699AA; // unlock seq 2
            // cache stuff here.
        __builtin_mtc0(_CP0_CONFIG, _CP0_CONFIG_SELECT, 0xA4010583);
        CHECONbits.PFMWS = 0x02; // 2 wait states for 48MHZ. if we go to 72 need 3
        CHECONbits.PREFEN = 0x03; // enable predictive cache in all regions

     // setup USB PLL
        UPLLCONbits.PLLIDIV = 0x07; // divide by 12 48/12 = 4*24 = 96/2 = 48
        UPLLCONbits.PLLODIV = 0x01; // divide by 2
        UPLLCONbits.PLLMULT = 0x07; // Multiply by 24

     // setup system PLL
        SPLLCONbits.PLLIDIV = 0x07; // 48/12 = 4
        SPLLCONbits.PLLMULT = 0x07; // 4*24 = 96Mhz
        SPLLCONbits.PLLODIV = 0x01; // 96Mhz/2 =48
        SPLLCONbits.PLLICLK = 0x00; // select the EC as input to SPLL

        OSCCONbits.UFRCEN = 0x00; // use primary pll as input to USB module
        OSCCONbits.NOSC = 0x03; // POSC EC
        OSCCONbits.OSWEN = 0x01; // Enable new OSC.

        BMXCONbits.BMXWSDRM = 0x0; // 0 wait states on RAM

        SYSKEY = 0x00; // relock

     
    This is my setup for the MX274 as I come up in FRC setup another part which provides a 48MHZ clock that goes to OSC1, then I do this.
     
    But after this code you have to sit and wait for the PLL to lock.
     
    Found another errata as the damn USB PLL does not show lock after this, either that is an errata or the USB module has to be enabled as well for that to become active.
     
    To check and see if the PLL's are locked you have to look at the CLKSTAT to see if the SPLLRDY bit is 1 before doing other code.
     
    The DDR PLL is weird as it is actually part of the coprocessor and you may have to look at that before reclocking the SYSKEY as that is in the CFGMPLL register. I would actually write all those variables inside the SYSKEY lock and then wait for the MPLLRDY bit to go true then lock the SYSKEY.
     
    All of this needs to be done early in the init phase of your code.
     
    Thanks,
    Gordon
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    cjohnson
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    Re: PIC32MZ DA FRC with DDR 2018/10/19 12:21:29 (permalink)
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    Gordon,
     
    Thanks for the reply.
     
    I've got it past the MPLLRDY bit, it's currently getting stuck waiting for the SCLLBPASS and SCLUBPASS bits to be set. It looks like I've got the clock signal portion figured out, but now the DDR PHY seems to be having a hard time starting up.
     
    Hmm. Not sure why those bits wouldn't be getting set if the DDR has a clock signal and the MPLL already has initialized.
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    Wavelength
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    Re: PIC32MZ DA FRC with DDR 2018/10/19 12:30:38 (permalink)
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    Colby,
     
    I would set the SCLEN bit after the DDR PLL is up and running that will cattle prod the self test I would think.
     
    Thanks,
    Gordon
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    cjohnson
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    Re: PIC32MZ DA FRC with DDR 2018/10/19 12:47:18 (permalink)
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    Gordon,
     
    Tried adding the SCLEN bit directly after the MPLL is initialized and no bueno. One thing I noticed when I first started this project, is that the DDR PHY init function fails if the clock is even a little bit different. I have never been able to get my setup to work on 200 MHz or 400. The best I've been able to get is 192 MHz. Going to try that speed again and see what happens.
     
    Just measured the clock signal going in to the OSC1I and it looks pretty good. Had my probe on 1X attenuation.
     

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    Wavelength
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    Re: PIC32MZ DA FRC with DDR 2018/10/19 13:03:29 (permalink)
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    Colby,
     
    It's only a 200Mhz part I think. Core: 200 MHz / 330 DMIPS MIPS32® microAptiv™
     
    Or do you mean the DDR2 spec to 400?
     
    Thanks,
    Gordon
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