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Wavelength
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2018/10/16 07:37:31 (permalink)
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Anybody little help with MX274 Cache registers

All,
 
I have been working on and off on a PLIB project with the PIC32MX274. Previously the designs were MX270 so I didn't want to start over again.
 
So I have the app linking with the cache currently disabled. But I am wondering if anyone has fooled around with the MX274 extended cache. I am running it at 48Mhz and realize that I need 2 wait states, but was wondering about the other options in the cache registers.
 
Thanks,
Gordon
#1
Howard Long
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Re: Anybody little help with MX274 Cache registers 2018/10/16 09:42:06 (permalink)
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I can't remember what this was for, but here is some code I wrote a while a go for a PIC32MX174F256B, the non-USB version of your device. It's derived from what Harmony MHC generates, and although it doesn't need any MHC bloat, it's a standalone main.c file, it will need the Harmony peripheral library and headers, see the first two lines of comments. 
 
Hope this helps.
 

// Include dir: c:/microchip/harmony/v2_05_01/framework/
// Lib: C:\microchip\harmony\v2_05_01\bin\framework\peripheral\PIC32MX795F512L_peripherals.a
// PIC32MX174F256B Configuration Bit Settings
// 'C' source line config statements
// DEVCFG3
// USERID = No Setting
#pragma config AI2C1 = OFF // Alternate I/O Select for I2C1 (I2C1 uses the SDA1/SCL1 pins)
#pragma config AI2C2 = OFF // Alternate I/O Select for I2C2 (I2C2 uses the SDA2/SCL2 pins)
#pragma config PMDL1WAY = OFF // Peripheral Module Disable Configuration (Allow multiple reconfigurations)
#pragma config IOL1WAY = OFF // Peripheral Pin Select Configuration (Allow multiple reconfigurations)
// DEVCFG2
#pragma config FPLLIDIV = DIV_2 // PLL Input Divider (2x Divider)
#pragma config FPLLMUL = MUL_18 // PLL Multiplier (18x Multiplier)
#pragma config FPLLICLK = PLL_FRC // System PLL Input Clock Selection (FRC is input to the System PLL)
#pragma config FPLLODIV = DIV_1 // System PLL Output Clock Divider (PLL Divide by 1)
#pragma config BOREN = OFF // Brown-Out Reset (BOR) Enable (Disable BOR)
#pragma config DSBOREN = OFF // Deep Sleep BOR Enable (Disable ZPBOR during Deep Sleep Mode)
#pragma config DSWDTPS = DSPS32 // Deep Sleep Watchdog Timer Postscaler (1:2^36)
#pragma config DSWDTOSC = LPRC // Deep Sleep WDT Reference Clock Selection (Select LPRC as DSWDT Reference clock)
#pragma config DSWDTEN = ON // Deep Sleep Watchdog Timer Enable (Enable DSWDT during Deep Sleep Mode)
#pragma config FDSEN = OFF // Deep Sleep Enable (Disable DSEN bit in DSCON)
// DEVCFG1
//#pragma config FNOSC = FRC // Oscillator Selection Bits (Fast RC Osc (FRC))
#pragma config FNOSC = SPLL // Oscillator Selection Bits (System PLL)
#pragma config FSOSCEN = OFF // Secondary Oscillator Enable (Disabled)
#pragma config IESO = OFF // Internal/External Switch Over (Disabled)
#pragma config POSCMOD = OFF // Primary Oscillator Configuration (Primary osc disabled)
#pragma config OSCIOFNC = ON // CLKO Output Signal Active on the OSCO Pin (Enabled)
#pragma config FPBDIV = DIV_1 // Peripheral Clock Divisor (Pb_Clk is Sys_Clk/1)
#pragma config FCKSM = CSECMD // Clock Switching and Monitor Selection (Clock Switch Enable, FSCM Disabled)
#pragma config WDTPS = PS1048576 // Watchdog Timer Postscaler (1:1048576)
#pragma config WDTSPGM = ON // Watchdog Timer Stop During Flash Programming (Watchdog Timer stops during Flash programming)
#pragma config WINDIS = OFF // Watchdog Timer Window Enable (Watchdog Timer is in Non-Window Mode)
#pragma config FWDTEN = OFF // Watchdog Timer Enable (WDT Disabled (SWDTEN Bit Controls))
#pragma config FWDTWINSZ = WINSZ_25 // Watchdog Timer Window Size (Window Size is 25%)
// DEVCFG0
#pragma config JTAGEN = OFF // JTAG Enable (JTAG Disabled)
#pragma config ICESEL = ICS_PGx2 // ICE/ICD Comm Channel Select (Communicate on PGEC2/PGED2)
#pragma config PWP = OFF // Program Flash Write Protect (Disable)
#pragma config SMCLR = MCLR_NORM // Soft Master Clear Enable (MCLR pin generates a normal system Reset)
#pragma config BWP = OFF // Boot Flash Write Protect bit (Protection Disabled)
#pragma config CP = OFF // Code Protect (Protection Disabled)
// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.
#include <xc.h>
#include <sys/attribs.h>
#include "peripheral/peripheral.h"
#include <stdint.h>
#define SYS_CLK_FREQUENCY 72000000
static void CPUInit(void)
{
// Note that cache is already configured by startup code
// C:\Program Files\Microchip\xc32\v1.42\pic32-libs\libpic32\stubs\pic32_init_cache.S

register unsigned long tmp = 0;
/* Set kseg0 coherency algorithm to "cacheable, non-coherent, write-back,
* write-allocate. This is needed for the prefetch buffer */
asm("mfc0 %0,$16,0" : "=r"(tmp));
tmp = (tmp & ~7) | 3;
asm("mtc0 %0,$16,0" :: "r" (tmp));

// Set up wait states
PLIB_PCACHE_WaitStateSet(PCACHE_ID_0,3); // Adjust as appropriate for memory and clock, 0 <=18MHz, 1 <=36MHz, 2 <=54MHz, 3 <=72MHz for PIC32MX1xx/2xx XLP

// Set up prefetch
if (PLIB_PCACHE_ExistsPrefetchEnable(PCACHE_ID_0))
{
PLIB_PCACHE_PrefetchEnableSet(PCACHE_ID_0, PLIB_PCACHE_PREFETCH_ENABLE_ALL);
}

/* Set the SRAM wait states to zero */
if (PLIB_BMX_ExistsDataRamWaitState(BMX_ID_0))
{
PLIB_BMX_DataRamWaitStateSet(BMX_ID_0, PLIB_BMX_DATA_RAM_WAIT_ZERO);
}

// Set up interrupt controller
PLIB_INT_MultiVectorSelect(INT_ID_0);
PLIB_INT_Enable(INT_ID_0);
}
void __attribute__((vector(_TIMER_2_VECTOR),interrupt(IPL7AUTO))) __Timer2Interrupt(void)
{
IFS0CLR=_IFS0_T2IF_MASK;
LATBINV=0x20; // Toggle LED
}
int main(void)
{
CPUInit();

TRISA=0;
TRISB=0;

// Set up timer 2
T2CON=0;
TMR2=0;
PR2= 1000; //SYS_CLK_FREQUENCY/1000; // 1 millisecond
IPC2bits.T2IP=7;
IPC2bits.T2IS=0;
IFS0CLR=0x100; // Atomic version of IFS0bits.T2IF=0;
IEC0bits.T2IE=1;
T2CONbits.ON=1;

while (1)
{
LATBSET=0x40;
LATBCLR=0x40;
// LATBbits.LATB6=1;
// LATBbits.LATB6=0;
Nop();
}
return 0;
}

#2
jg_ee
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Re: Anybody little help with MX274 Cache registers 2018/10/16 10:29:09 (permalink)
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Here is some more code for reference. No guarantees!
 
 
void pic32_startup(void) {
    //This function is meant to replace PIC32ConfigPerformance from old plib

    __builtin_disable_interrupts();

    SYSKEY = 0xAA996655;
    SYSKEY = 0x556699AA;

    //enable the cache, other configs as default
    __builtin_mtc0(_CP0_CONFIG, _CP0_CONFIG_SELECT, 0xa4010583);

    CHECONbits.PFMWS = 0x2; //0 for 0-30 MHz, 1 for 31-60 MHz, 2 for 61-80 MHz (PIC32MX795F512L)
    CHECONbits.PREFEN = 0x3; //enable predictive cache for both mem regions
    BMXCONbits.BMXWSDRM = 0x0; //0 data ram wait states
    INTCONbits.MVEC = 1; //enable multi vector

    SYSKEY = 0x0;

    __builtin_enable_interrupts();
}

#3
Wavelength
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Re: Anybody little help with MX274 Cache registers 2018/10/16 10:54:27 (permalink)
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Justin,
Thanks, yea that is what I needed.
Gordon
 
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NKurzman
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Re: Anybody little help with MX274 Cache registers 2018/10/16 11:25:26 (permalink)
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Another option is to Use MCC or Harmony , then look at what it does.
#5
Wavelength
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Re: Anybody little help with MX274 Cache registers 2018/10/16 11:32:53 (permalink)
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NK,
Harmony sets the waits states to 3 and that's it.
 
0x0000033
 
Thanks,
G.
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Howard Long
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Re: Anybody little help with MX274 Cache registers 2018/10/17 00:50:00 (permalink)
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See the code I posted above for what Harmony generates.
 
 // Set up wait states
PLIB_PCACHE_WaitStateSet(PCACHE_ID_0,3); // Adjust as appropriate for memory and clock, 0 <=18MHz, 1 <=36MHz, 2 <=54MHz, 3 <=72MHz for PIC32MX1xx/2xx XLP
[/code]
#7
Wavelength
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Re: Anybody little help with MX274 Cache registers 2018/10/17 06:21:34 (permalink)
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Howard,
 
Thanks do remember I am using PLIB.
 
Gordon
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jg_ee
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Re: Anybody little help with MX274 Cache registers 2018/10/17 06:46:07 (permalink)
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Gordon,
 
Also in case you haven't found it yet, the CP0 register from that __builtin_mtc0 function call is CP0 Register 16, which you can find what all the bits mean in the PIC32 Family Reference Manual Section 2.
 
Your wait states you need will be documented in the electrical section of your specific PIC datasheet.
 
Justin
#9
Wavelength
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Re: Anybody little help with MX274 Cache registers 2018/10/17 08:06:55 (permalink)
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Justin,
 
Thanks was just going to pass that by. So in the older MX270 when they set the Kseq this is really what they were doing since it didn't have the expanded caching?
 
Ok I will add that into the code so I basically have this setup now:
 
SYSKEY = 0xAA996655;
SYSKEY = 0x556699AA;

__builtin_mtc0(_CP0_CONFIG, _CP0_CONFIG_SELECT, 0xA4010583);
CHECONbits.PFMWS = 0x2; // 2 waits for 48Mhz
CHECONbits.PREFEN = 0x3;
// now update the oscillator from internal to external.
OSCCONbits.NOSC = 0x03;  // oscillator = EC
OSCCONbits.OWEN = 0x01; // enable the new oscillator
UPLLCONbits.PLLMULT = 0x07; // (4x24)/2 = 48Mhz

SYSKEY = 0x0;

 
Thanks,
Gordon
#10
jg_ee
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Re: Anybody little help with MX274 Cache registers 2018/10/17 08:48:02 (permalink)
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Gordon,
 
Looks OK to me, I think the core and pre-fetch is identical to the PIC32MX795 code I shared.  Also, I can't find where it is explained anywhere in the documentation, but I think if you are not executing instructions from RAM you might as well change the SRAM wait states to zero instead of the default one?  I would imagine this could make a significant performance improvement depending on what you are doing.  The old SYSTEMConfigPerformance() function always set it to zero:
 
 
extern inline unsigned int __attribute__((always_inline)) SYSTEMConfigPerformance(unsigned int sys_clock)
{
    // set up the wait states
    unsigned int pb_clk;
#ifdef _PCACHE
    unsigned int cache_status;
#endif
    unsigned int int_status;

    pb_clk = SYSTEMConfigWaitStatesAndPB(sys_clock);

    int_status=INTDisableInterrupts();

    mBMXDisableDRMWaitState();

#ifdef _PCACHE
    cache_status = mCheGetCon();
    cache_status |= CHE_CONF_PF_ALL;
    mCheConfigure(cache_status);
    CheKseg0CacheOn();
#endif

    INTRestoreInterrupts(int_status);

    return pb_clk;

}

 
 
Also I did not look closely into your oscillator code you added, but I recall on PIC24 at least you should wait for a PLL lock bit before continuing execution after switching (may be different on PIC32).
 
Justin
#11
Howard Long
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Re: Anybody little help with MX274 Cache registers 2018/10/17 09:23:18 (permalink)
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Wavelength
Howard,
 
Thanks do remember I am using PLIB.
 
Gordon

No worries, as I'm sure you know PLIB was deprecated a while back, I assumed the equivalent peripheral library functions out of Harmony would also be helpful, provided in a way that you don't have to suffer the indignity of fighting with MHC ;-)
 
I too prefer bare metal, but for a few things, like this, I let Harmony generate the boilerplate and then lift the relevant bits into standalone project without being dictated to by Harmony's coding strait jacket.
 
post edited by Howard Long - 2018/10/17 09:31:19
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Wavelength
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Re: Anybody little help with MX274 Cache registers 2018/10/17 09:23:45 (permalink)
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Justin,
 
The code right after the syskey lock waits for the PLL to lock. I come up with the FRC then enable another part which has the SYSCLK wired to the OSC pin. After that is enabled I wait till it settles then change the clock over to the external EC.
 
I will add the sram waits.
 
Trying to debug the damn thing now and it's not coming up, probably some pragma difference.
 
Thanks,
Gordon
#13
Wavelength
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Re: Anybody little help with MX274 Cache registers 2018/10/17 09:54:34 (permalink)
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Howard,
 
Ok your code thru me for a loop.
 
Having 2 problems right now, something in my pragma is causing it not to start. I will look at those.
 
The second is that I am using the FS USB and there is no doc or DEVCFGx for UPLLMULT and UPLLODIV.
 
Thanks,
Gordon
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qhb
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Re: Anybody little help with MX274 Cache registers 2018/10/17 14:31:55 (permalink)
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I see you solved the last issue at https://www.microchip.com/forums/FindPost/1071798
 

Nearly there...
#15
Wavelength
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Re: Anybody little help with MX274 Cache registers 2018/10/18 09:58:55 (permalink)
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Howard,
 
I am having a problem with IO on the A3, I have OSCIOFNC = 1 in my DEVCFG, but in the debugger I can see the TRIS bit for A3 is defaulting to 1, no matter what I set it for. Is there something else I am missing? That seemed to work on the MX270, but not on the MX274??
 
They really should have called this family something different like MX280 or something there is so much difference between the MX270 and MX274. Stupid assumption on my part that they would be similar.
 
Thanks,
Gordon
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Wavelength
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Re: Anybody little help with MX274 Cache registers 2018/10/18 10:06:51 (permalink)
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Howard,
Forget it figured it out, was not A3 giving me a problem it was A4. Now I see hidden in the notes that this pin can only be used as an INPUT.
 
Thanks,
Gordon
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Howard Long
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Re: Anybody little help with MX274 Cache registers 2018/10/19 01:32:57 (permalink)
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Wavelength
Howard,
 
The second is that I am using the FS USB and there is no doc or DEVCFGx for UPLLMULT and UPLLODIV.
 



I'm not in the the lab today, so don't have access to the part or equipment with me to give you an answer immediately.
 
Please note that the values would be dependent on your clock source. You cannot directly use the FRC as a reference for the USB clock, it's not within specification, so you should either use a crystal or an external oscillator POSC.
 
With the XLP Starter Kit that contains a PIC32MX274F256D, it has a 12MHz EC POSC and uses this scheme from the cdc_com_port_dual Harmony example:
 
DEVCFG1.POSCMOD: EC => 12MHz
DEVCFG2.UPLLIDIV: DIV_3 => 4MHz
UPLLCONbits.PLLMULT: 24 => 96MHz
UPLLCONbits.PLLODIV: DIV_2 => 48MHz
 
System_init.c:
 

...
#pragma config POSCMOD = EC
...
#pragma config UPLLIDIV = DIV_3
#pragma config UPLLEN = ON
...

 
sys_clk_pic32mx.c:
 

...
void SYS_CLK_Initialize( const SYS_CLK_INIT const * clkInit )
{
SYS_DEVCON_SystemUnlock ( );
...
/* Configure UPLL */
PLIB_OSC_UPLLMultiplierSelect(OSC_ID_0, 24);
PLIB_OSC_UPLLOutputDivisorSet(OSC_ID_0, OSC_UPLL_OUT_DIV_2);
PLIB_OSC_UsbClockSourceSelect (OSC_ID_0, SYS_OSC_USBCLK_PRIMARY);
...
SYS_DEVCON_SystemLock ( );
}
...

 
post edited by Howard Long - 2018/10/19 01:38:51
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Wavelength
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Re: Anybody little help with MX274 Cache registers 2018/10/19 06:42:01 (permalink)
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Howard,
 
Thanks, yes I had to do all that in the 5 products I did with the MX274. What was throwing me off was that the data sheet did not have specific UPLLODIV and UPLLMULT as options so I thought it was omitted.
 
I then found the UPLLCON register and the naming convention and implemented all that.
 
Also sent over a number of minor problems with the data sheet over to corporate, like RA4, RB4 in the IO map show them as I/O and really they can be inputs and some typo's that are a little funny.
 
But thanks for the AI2C stuff in your original post. I did not have those set in the first code I was using and the I2C just sat there. Now that is working, but for some reason my system clock generated from another part is not starting up. Oh hardware, lets put 118 parts in a 1.5x0.5 board and try and debug it. Fun fun fun
 
Thanks,
Gordon
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Howard Long
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Re: Anybody little help with MX274 Cache registers 2018/10/19 08:32:55 (permalink)
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Wavelength
Oh hardware, lets put 118 parts in a 1.5x0.5 board and try and debug it. Fun fun fun

FWIW, my first application with this series of PIC32 had 210 parts on 0.735 x 2.42 inch board, on a 6 layer double load. I feel your pain, I didn't know until routing the last couple of parts it was going to even fit.
 
Edit: to put it into perspective, I originally used a 44 pin D part as I needed the extra IOs, but there wasn't enough routing room, even with 6 layers, to get 8 GPIOs down to the far end. So I dropped down to a 28 pin B part and added an I2C IO expander where it was needed, it took less overall board space but was slightly more expensive. The engineering driving factor was the enclosure which wasn't really negotiable, the cost of re-tooling for a slightly larger custom enclosure was far more than switching in an IO expander.
 
post edited by Howard Long - 2018/10/19 08:39:40
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