AnsweredHot!33CH MSI FIFO with DMA

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Weydert
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2018/09/15 10:53:21 (permalink)
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33CH MSI FIFO with DMA

hi,
has anyone got the Master-Slave-Interface FIFO got working with DMA?
I tried 3 differnet ways and got the same problem.
The general Setup is: Slave writes to FIFO and Master awaits data.
1) Master sets up FIFO and DMA
2) Master starts Slave
3) Slave inits (or not) DMA and sends data to FIFO
 
A) Master FIFO configured to get "data ready" Interrupt after FIFO 100% full (32 words)
    Master DMA triggered by "data ready" IRQ, word-count=32
    Slave writes 32 words to FIFO (without DMA) and then does nothing.
 
   Result A: The DMA Interrupt fires but the the DMA is not finished, only 2 or 3 words are transfered and the OVRUNIF is set:
  "The DMA channel is triggered while it is still completing the operation based on the previous trigger"
B) Master FIFO configured to get "data ready" Interrupt after one word in FIFO.
    Master DMA triggered by "data ready" IRQ, word-count=64
    Slave writes 64 words to FIFO, checking the FIFO to be empty before writing (SWFEMPTY=1)
 
   Result B: Same as A, OVRUNIF set after 2 or 3 words.
 
C) Like explained in DS70005278B: USING A FIFO WITH DMA
    Master FIFO configured to get "data ready" Interrupt after one word in FIFO.
    Master DMA triggered by "data ready" IRQ, word-count=64
    Slave DMA configured in single shot mode, triggerd by "MSI Slave Write FIFO Empty IRQ"
 
    Result C: Same as A and B: OVRUNIF set after 2 or 3 words.
 
Not that I really need DMA at this time, but I thought it would be an easy lesson just to check how it works.
 
By the way, I can debug only Master or Slave at the same time (only one debugger availble) and this makes it difficult to check whats going on.
 
Is anyone working on FIFO with DMA and has got other experience?
Regards
Rainer
 
Device: dsPIC33CH128MP506 (S1), Master and Slave running at same Fcyc.
#1
Weydert
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Re: 33CH MSI FIFO with DMA 2018/09/16 08:25:26 (permalink)
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Bad news and good news:
1) Could still not get FIFO working with DMA.
2) Could get Mailbox working with DMA.
 
Setup for Mailbox transfer:
Configuration bits:
Mailbox 0 direction: slave to master
Handshake A  assigned to Mailbox 0
Handshake A enabled
 
Code:
Master:
DMA: from MSI1MBX0D to buffer, single shot, count=64, trigger=MSIA IRQ
Slave:
DMA: from buffer to  SI1MBX0D, single shot, count=64, trigger=MSIA IRQ
 
Debugging the slave and using the Stopwatch it shows me about 645 cycles from starting the transfer (setting the CHREQ bit (former FORCE bit)) until DMA interrupt is fired after 64 words.
Changing buffer-size and transfer-count to 128 word transfer was finished in 1158 cycles.
(during transfer neighter master nor slave accessed any peripheral, just staying in a loop)
 
Also there is no need any more for me to use the FIFO i'm still interested in your FIFO with DMA experience
 
Regards
Rainer
 
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Frytki
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Re: 33CH MSI FIFO with DMA 2018/12/18 04:49:50 (permalink) ☼ Best Answerby Weydert 2018/12/18 08:44:22
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Weydert thank you for share your tests. I experimenting with MSI in dsPIC33CH128MP508 and I have problems also. Ultimately, I need to use DMA but a tested also without it.
FIFO transmission works only from master to slave(works also with DMA), otherwise data is sent by the slave but nothing is received by the master. The code is valid with example in Reference Manual.

I also tested the mailbox, master to slave works, otherwise not. But when I tried to handle it through DMA, I could not get an interrupt

Has anyone managed to run communication on both sides?
Regards, Adam
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Weydert
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Re: 33CH MSI FIFO with DMA 2018/12/18 08:54:03 (permalink)
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hi,
I have no problem to transfer data from slave to master (using interrupts and byte-copy), neither by fifo nor by mailbox. You could tell us which code example you are using. Especially post a picture of the configuration bits.
(and: do you use hardware or simulator? Nothing is working with the simulator for this device)
Regards
Rainer
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Frytki
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Re: 33CH MSI FIFO with DMA 2018/12/21 08:06:13 (permalink)
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Ok, I have simple code. Master -> Slave works, inversely not. I can debug one of the core. I don't use the simulator. The cores work at different speeds, the same speed - without changes.
Please help.

Master code:
 volatile uint16_t temp;
 MSI1FIFOCSbits.WFEN=1;
 MSI1FIFOCSbits.RFEN=1; // FIFO SLAVE->MASTER NOT WORK
 while(MSI1FIFOCSbits.WFEN==0); // wait till Master enables the Masters Read FIFO
 while(MSI1FIFOCSbits.RFEN==0);
 MWSRFDATA = 0b010101;
 while(1)
 {
  if(temp = MRSWFDATA) // it's never true
  {
   while(1);
  }
 }


Slave code:
 volatile uint16_t temp;
 while(SI1FIFOCSbits.SWFEN==0);
 while(SI1FIFOCSbits.SRFEN==0);
 SWMRFDATA = 0b101010;
 while(1)
 {
  if(temp = SRMWFDATA)
  {
   while(1);
  }
 }


Configuration bits:
// DSPIC33CH128MP508 Configuration Bit Settings
// 'C' source line config statements
// FSEC
#pragma config BWRP = OFF // Boot Segment Write-Protect bit (Boot Segment may be written)
#pragma config BSS = DISABLED // Boot Segment Code-Protect Level bits (No Protection (other than BWRP))
#pragma config BSEN = OFF // Boot Segment Control bit (No Boot Segment)
#pragma config GWRP = OFF // General Segment Write-Protect bit (General Segment may be written)
#pragma config GSS = DISABLED // General Segment Code-Protect Level bits (No Protection (other than GWRP))
#pragma config CWRP = OFF // Configuration Segment Write-Protect bit (Configuration Segment may be written)
#pragma config CSS = DISABLED // Configuration Segment Code-Protect Level bits (No Protection (other than CWRP))
#pragma config AIVTDIS = OFF // Alternate Interrupt Vector Table bit (Disabled AIVT)

// FBSLIM
#pragma config BSLIM = 0x1FFF // Boot Segment Flash Page Address Limit bits (Boot Segment Flash page address limit)

// FSIGN

// FOSCSEL
#pragma config FNOSC = FRC // Oscillator Source Selection (Internal Fast RC (FRC))
#pragma config IESO = OFF // Two-speed Oscillator Start-up Enable bit (Start up with user-selected oscillator source)

// FOSC
#pragma config POSCMD = XT // Primary Oscillator Mode Select bits (XT Crystal Oscillator Mode)
#pragma config OSCIOFNC = OFF // OSC2 Pin Function bit (OSC2 is clock output)
#pragma config FCKSM = CSECMD // Clock Switching Mode bits (Clock switching is enabled,Fail-safe Clock Monitor is disabled)
#pragma config PLLKEN = PLLKEN_ON // PLLKEN (PLLKEN_ON)
#pragma config XTCFG = G3 // XT Config (24-32 MHz crystals)
#pragma config XTBST = ENABLE // XT Boost (Boost the kick-start)

// FWDT
#pragma config RWDTPS = PS1048576 // Run Mode Watchdog Timer Post Scaler select bits (1:1048576)
#pragma config RCLKSEL = LPRC // Watchdog Timer Clock Select bits (Always use LPRC)
#pragma config WINDIS = ON // Watchdog Timer Window Enable bit (Watchdog Timer operates in Non-Window mode)
#pragma config WDTWIN = WIN25 // Watchdog Timer Window Select bits (WDT Window is 25% of WDT period)
#pragma config SWDTPS = PS1048576 // Sleep Mode Watchdog Timer Post Scaler select bits (1:1048576)
#pragma config FWDTEN = ON // Watchdog Timer Enable bit (WDT enabled in hardware)

// FICD
#pragma config ICS = PGD1 // ICD Communication Channel Select bits (Communicate on PGEC1 and PGED1)
#pragma config JTAGEN = OFF // JTAG Enable bit (JTAG is disabled)

// FDMTIVTL
#pragma config DMTIVTL = 0xFFFF // Dead Man Timer Interval low word (Lower 16 bits of 32 bitDMT window interval (0-0xFFFF))

// FDMTIVTH
#pragma config DMTIVTH = 0xFFFF // Dead Man Timer Interval high word (Uper 16 bits of 32 bitDMT window interval (0-0xFFFF))

// FDMTCNTL
#pragma config DMTCNTL = 0xFFFF // Lower 16 bits of 32 bit DMT instruction count time-out value (0-0xFFFF) (Lower 16 bits of 32 bit DMT instruction count time-out value (0-0xFFFF))

// FDMTCNTH
#pragma config DMTCNTH = 0xFFFF // Upper 16 bits of 32 bit DMT instruction count time-out value (0-0xFFFF) (Upper 16 bits of 32 bit DMT instruction count time-out value (0-0xFFFF))

// FDMT
#pragma config DMTDIS = OFF // Dead Man Timer Disable bit (Dead Man Timer is Disabled and can be enabled by software)

// FDEVOPT
#pragma config ALTI2C1 = OFF // Alternate I2C1 Pin bit (I2C1 mapped to SDA1/SCL1 pins)
#pragma config ALTI2C2 = OFF // Alternate I2C2 Pin bit (I2C2 mapped to SDA2/SCL2 pins)
#pragma config SMBEN = SMBUS // SM Bus Enable (SMBus input threshold is enabled)
#pragma config SPI2PIN = PPS // SPI2 Pin Select bit (SPI2 uses I/O remap (PPS) pins)

// FALTREG
#pragma config CTXT1 = OFF // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits (Not Assigned)
#pragma config CTXT2 = OFF // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 2 bits (Not Assigned)
#pragma config CTXT3 = OFF // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 3 bits (Not Assigned)
#pragma config CTXT4 = OFF // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 4 bits (Not Assigned)

// FMBXM
#pragma config MBXM0 = S2M // Mailbox 0 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM1 = S2M // Mailbox 1 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM2 = S2M // Mailbox 2 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM3 = S2M // Mailbox 3 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM4 = S2M // Mailbox 4 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM5 = S2M // Mailbox 5 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM6 = S2M // Mailbox 6 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM7 = S2M // Mailbox 7 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM8 = S2M // Mailbox 8 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM9 = S2M // Mailbox 9 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM10 = S2M // Mailbox 10 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM11 = S2M // Mailbox 11 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM12 = S2M // Mailbox 12 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM13 = S2M // Mailbox 13 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM14 = S2M // Mailbox 14 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM15 = S2M // Mailbox 15 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))

// FMBXHS1
#pragma config MBXHSA = MBX15 // Mailbox handshake protocol block A register assignment (MSIxMBXD15 assigned to mailbox handshake protocol block A)
#pragma config MBXHSB = MBX15 // Mailbox handshake protocol block B register assignment (MSIxMBXD15 assigned to mailbox handshake protocol block B)
#pragma config MBXHSC = MBX15 // Mailbox handshake protocol block C register assignment (MSIxMBXD15 assigned to mailbox handshake protocol block C)
#pragma config MBXHSD = MBX15 // Mailbox handshake protocol block D register assignment (MSIxMBXD15 assigned to mailbox handshake protocol block D)

// FMBXHS2
#pragma config MBXHSE = MBX15 // Mailbox handshake protocol block E register assignment (MSIxMBXD15 assigned to mailbox handshake protocol block E)
#pragma config MBXHSF = MBX15 // Mailbox handshake protocol block F register assignment (MSIxMBXD15 assigned to mailbox handshake protocol block F)
#pragma config MBXHSG = MBX15 // Mailbox handshake protocol block G register assignment (MSIxMBXD15 assigned to mailbox handshake protocol block G)
#pragma config MBXHSH = MBX15 // Mailbox handshake protocol block H register assignment (MSIxMBXD15 assigned to mailbox handshake protocol block H)

// FMBXHSEN
#pragma config HSAEN = OFF // Mailbox A data flow control protocol block enable (Mailbox data flow control handshake protocol block disabled.)
#pragma config HSBEN = OFF // Mailbox B data flow control protocol block enable (Mailbox data flow control handshake protocol block disabled.)
#pragma config HSCEN = OFF // Mailbox C data flow control protocol block enable (Mailbox data flow control handshake protocol block disabled.)
#pragma config HSDEN = OFF // Mailbox D data flow control protocol block enable (Mailbox data flow control handshake protocol block disabled.)
#pragma config HSEEN = OFF // Mailbox E data flow control protocol block enable (Mailbox data flow control handshake protocol block disabled.)
#pragma config HSFEN = OFF // Mailbox F data flow control protocol block enable (Mailbox data flow control handshake protocol block disabled.)
#pragma config HSGEN = OFF // Mailbox G data flow control protocol block enable (Mailbox data flow control handshake protocol block disabled.)
#pragma config HSHEN = OFF // Mailbox H data flow control protocol block enable (Mailbox data flow control handshake protocol block disabled.)

// FCFGPRA0
#pragma config CPRA0 = MSTR // Pin RA0 Ownership Bits (Master core owns pin.)
#pragma config CPRA1 = MSTR // Pin RA1 Ownership Bits (Master core owns pin.)
#pragma config CPRA2 = MSTR // Pin RA2 Ownership Bits (Master core owns pin.)
#pragma config CPRA3 = MSTR // Pin RA3 Ownership Bits (Master core owns pin.)
#pragma config CPRA4 = MSTR // Pin RA4 Ownership Bits (Master core owns pin.)

// FCFGPRB0
#pragma config CPRB0 = MSTR // Pin RB0 Ownership Bits (Master core owns pin.)
#pragma config CPRB1 = MSTR // Pin RB1 Ownership Bits (Master core owns pin.)
#pragma config CPRB2 = MSTR // Pin RB2 Ownership Bits (Master core owns pin.)
#pragma config CPRB3 = MSTR // Pin RB3 Ownership Bits (Master core owns pin.)
#pragma config CPRB4 = MSTR // Pin RB4 Ownership Bits (Master core owns pin.)
#pragma config CPRB5 = MSTR // Pin RB5 Ownership Bits (Master core owns pin.)
#pragma config CPRB6 = MSTR // Pin RB6 Ownership Bits (Master core owns pin.)
#pragma config CPRB7 = MSTR // Pin RB7 Ownership Bits (Master core owns pin.)
#pragma config CPRB8 = MSTR // Pin RB8 Ownership Bits (Master core owns pin.)
#pragma config CPRB9 = MSTR // Pin RB9 Ownership Bits (Master core owns pin.)
#pragma config CPRB10 = MSTR // Pin RB10 Ownership Bits (Master core owns pin.)
#pragma config CPRB11 = MSTR // Pin RB11 Ownership Bits (Master core owns pin.)
#pragma config CPRB12 = MSTR // Pin RB12 Ownership Bits (Master core owns pin.)
#pragma config CPRB13 = MSTR // Pin RB13 Ownership Bits (Master core owns pin.)
#pragma config CPRB14 = MSTR // Pin RB14 Ownership Bits (Master core owns pin.)
#pragma config CPRB15 = MSTR // Pin RB15 Ownership Bits (Master core owns pin.)

// FCFGPRC0
#pragma config CPRC0 = MSTR // Pin RC0 Ownership Bits (Master core owns pin.)
#pragma config CPRC1 = MSTR // Pin RC1 Ownership Bits (Master core owns pin.)
#pragma config CPRC2 = MSTR // Pin RC2 Ownership Bits (Master core owns pin.)
#pragma config CPRC3 = MSTR // Pin RC3 Ownership Bits (Master core owns pin.)
#pragma config CPRC4 = MSTR // Pin RC4 Ownership Bits (Master core owns pin.)
#pragma config CPRC5 = MSTR // Pin RC5 Ownership Bits (Master core owns pin.)
#pragma config CPRC6 = MSTR // Pin RC6 Ownership Bits (Master core owns pin.)
#pragma config CPRC7 = MSTR // Pin RC7 Ownership Bits (Master core owns pin.)
#pragma config CPRC8 = MSTR // Pin RC8 Ownership Bits (Master core owns pin.)
#pragma config CPRC9 = MSTR // Pin RC9 Ownership Bits (Master core owns pin.)
#pragma config CPRC10 = MSTR // Pin RC10 Ownership Bits (Master core owns pin.)
#pragma config CPRC11 = MSTR // Pin RC11 Ownership Bits (Master core owns pin.)
#pragma config CPRC12 = MSTR // Pin RC12 Ownership Bits (Master core owns pin.)
#pragma config CPRC13 = MSTR // Pin RC13 Ownership Bits (Master core owns pin.)
#pragma config CPRC14 = MSTR // Pin RC14 Ownership Bits (Master core owns pin.)
#pragma config CPRC15 = MSTR // Pin RC15 Ownership Bits (Master core owns pin.)

// FCFGPRD0
#pragma config CPRD0 = MSTR // Pin RD0 Ownership Bits (Master core owns pin.)
#pragma config CPRD1 = MSTR // Pin RD1 Ownership Bits (Master core owns pin.)
#pragma config CPRD2 = MSTR // Pin RD2 Ownership Bits (Master core owns pin.)
#pragma config CPRD3 = MSTR // Pin RD3 Ownership Bits (Master core owns pin.)
#pragma config CPRD4 = MSTR // Pin RD4 Ownership Bits (Master core owns pin.)
#pragma config CPRD5 = MSTR // Pin RD5 Ownership Bits (Master core owns pin.)
#pragma config CPRD6 = MSTR // Pin RD6 Ownership Bits (Master core owns pin.)
#pragma config CPRD7 = MSTR // Pin RD7 Ownership Bits (Master core owns pin.)
#pragma config CPRD8 = MSTR // Pin RD8 Ownership Bits (Master core owns pin.)
#pragma config CPRD9 = MSTR // Pin RD9 Ownership Bits (Master core owns pin.)
#pragma config CPRD10 = MSTR // Pin RD10 Ownership Bits (Master core owns pin.)
#pragma config CPRD11 = MSTR // Pin RD11 Ownership Bits (Master core owns pin.)
#pragma config CPRD12 = MSTR // Pin RD12 Ownership Bits (Master core owns pin.)
#pragma config CPRD13 = MSTR // Pin RD13 Ownership Bits (Master core owns pin.)
#pragma config CPRD14 = MSTR // Pin RD14 Ownership Bits (Master core owns pin.)
#pragma config CPRD15 = MSTR // Pin RD15 Ownership Bits (Master core owns pin.)

// FCFGPRE0
#pragma config CPRE0 = MSTR // Pin RE0 Ownership Bits (Master core owns pin.)
#pragma config CPRE1 = MSTR // Pin RE1 Ownership Bits (Master core owns pin.)
#pragma config CPRE2 = MSTR // Pin RE2 Ownership Bits (Master core owns pin.)
#pragma config CPRE3 = MSTR // Pin RE3 Ownership Bits (Master core owns pin.)
#pragma config CPRE4 = MSTR // Pin RE4 Ownership Bits (Master core owns pin.)
#pragma config CPRE5 = MSTR // Pin RE5 Ownership Bits (Master core owns pin.)
#pragma config CPRE6 = MSTR // Pin RE6 Ownership Bits (Master core owns pin.)
#pragma config CPRE7 = MSTR // Pin RE7 Ownership Bits (Master core owns pin.)
#pragma config CPRE8 = MSTR // Pin RE8 Ownership Bits (Master core owns pin.)
#pragma config CPRE9 = MSTR // Pin RE9 Ownership Bits (Master core owns pin.)
#pragma config CPRE10 = MSTR // Pin RE10 Ownership Bits (Master core owns pin.)
#pragma config CPRE11 = MSTR // Pin RE11 Ownership Bits (Master core owns pin.)
#pragma config CPRE12 = MSTR // Pin RE12 Ownership Bits (Master core owns pin.)
#pragma config CPRE13 = MSTR // Pin RE13 Ownership Bits (Master core owns pin.)
#pragma config CPRE14 = MSTR // Pin RE14 Ownership Bits (Master core owns pin.)
#pragma config CPRE15 = MSTR // Pin RE15 Ownership Bits (Master core owns pin.)

// FS1OSCSEL
#pragma config S1FNOSC = FRC // Oscillator Source Selection (Internal Fast RC (FRC))
#pragma config S1IESO = OFF // Two-speed Oscillator Start-up Enable bit (Start up with user-selected oscillator source)

// FS1OSC
#pragma config S1OSCIOFNC = OFF // Slave OSC2 Pin Function bit (OSC2 is clock output)
#pragma config S1FCKSM = CSECMD // Clock Switching Mode bits (Clock switching is enabled,Fail-safe Clock Monitor is disabled)
#pragma config S1PLLKEN = S1PLLKEN_ON // S1PLLKEN (S1PLLKEN_ON)

// FS1WDT
#pragma config S1RWDTPS = PS1048576 // Run Mode Watchdog Timer Post Scaler select bits (1:1048576)
#pragma config S1RCLKSEL = LPRC // Watchdog Timer Clock Select bits (Always use LPRC)
#pragma config S1WINDIS = ON // Watchdog Timer Window Enable bit (Watchdog Timer operates in Non-Window mode)
#pragma config S1WDTWIN = WIN25 // Watchdog Timer Window Select bits (WDT Window is 25% of WDT period)
#pragma config S1SWDTPS = PS1048576 // Sleep Mode Watchdog Timer Post Scaler select bits (1:1048576)
#pragma config S1FWDTEN = ON // Watchdog Timer Enable bit (WDT enabled in hardware)

// FS1ICD
#pragma config S1ICS = PGD1 // ICD Communication Channel Select bits (Communicate on PGEC1 and PGED1)
#pragma config S1ISOLAT = OFF // Isolate the Slave core subsystem from the master subsystem during Debug (The slave can only operate if the SLVEN bit in the MSI is set.)
#pragma config S1NOBTSWP = OFF // BOOTSWP Instruction Enable/Disable bit (BOOTSWP instruction is disabled)

// FS1DEVOPT
#pragma config S1ALTI2C1 = OFF // Alternate I2C1 Pin bit (I2C1 mapped to SDA1/SCL1 pins)
#pragma config S1SPI1PIN = PPS // S1 SPI1 Pin Select bit (Slave SPI1 uses I/O remap (PPS) pins)
#pragma config S1SSRE = ON // Slave Slave Reset Enable (Slave generated resets will reset the Slave Enable Bit in the MSI module)
#pragma config S1MSRE = ON // Master Slave Reset Enable (The master software oriented RESET events (RESET Op-Code, Watchdog timeout, TRAP reset, illegalInstruction) will also cause the slave subsystem to reset.)

// FS1ALTREG
#pragma config S1CTXT1 = OFF // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits (Not Assigned)
#pragma config S1CTXT2 = OFF // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 2 bits (Not Assigned)
#pragma config S1CTXT3 = OFF // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 3 bits (Not Assigned)
#pragma config S1CTXT4 = OFF // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 4 bits (Not Assigned)

// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.

 
Regards, Adam
#5
Weydert
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Re: 33CH MSI FIFO with DMA 2018/12/21 10:34:58 (permalink)
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hi,
a first bug may be
'if(temp = SRMWFDATA)'
It will not do what you expect. What about '=='?
 
Where is 'temp' set? Within Interrupt ?
 
I don't see where you wait for data to be available in the FIFO. Wait until the Receiver FIFO is not empty before reading data from the FIFO.
 
Regards
Rainer
#6
Frytki
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Re: 33CH MSI FIFO with DMA 2018/12/21 11:14:35 (permalink)
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Yes... but it was on purpose. Writing and then checking. I did as you say but still unchanged.
 
 
 volatile uint16_t temp;
 MSI1FIFOCSbits.WFEN=1;
 MSI1FIFOCSbits.RFEN=1; // FIFO SLAVE->MASTER NOT WORK
 while(MSI1FIFOCSbits.WFEN==0); // wait till Master enables the Masters Read FIFO
 while(MSI1FIFOCSbits.RFEN==0);
 MWSRFDATA = 0b010101;
 temp = 0;
 while(1)
 {
  if(MSI1FIFOCSbits.RFEMPTY == 0) // it's never true
  {
   temp = MRSWFDATA;
   while(1);
  }
 }

 
#7
Weydert
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Re: 33CH MSI FIFO with DMA 2018/12/22 02:14:14 (permalink) ☄ Helpfulby Frytki 2018/12/23 08:22:56
5 (1)
ok,
I think you read AN2721 'Getting started with Dual Core'.
From the different MODES OF DEBUG/PROGRAM OPERATIONS in Table 1 you use 'Normal Mode' where the Master Core can be debugged and the Slave is programmed and started by the Master.
Did you start the program and start the Slave with _program_slave(...,...,...) and _start_slave() ?
Or how else do you know that the Slave is programmed and running?
 
Regards
Rainer
#8
Weydert
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Re: 33CH MSI FIFO with DMA 2018/12/22 05:03:17 (permalink) ☄ Helpfulby Frytki 2018/12/23 08:23:03
4.5 (2)
Hi,
I attach some files:
The purpose is to run a Master-Stub and debug the Slave:
Master-Stub:
-init FIFO
-send word 0x1234 to Slave
-wait until Slave answers with one word in FIFO (this is what didn't work ...)
-increment received word by one and send to slave.
 
Slave:
-wait for Master FIFO init done
-wait for data in FIFO and read
-increment data by one and send to Master
-await answer from Master.
 
When I debug the Slave, I see the value 0x1234 arriving in FIFO. (as you do)
When sending back 0x1235 to Master you can't see what happens within the Master BUT
if the Slave waits for another word from Master and gets a word you know that the Master has answered.
In my hardware the Slave receives 0x1236 - as expected.
 
Regards
Rainer
#9
Frytki
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Re: 33CH MSI FIFO with DMA 2018/12/23 08:24:04 (permalink)
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Ajjj, yes. The slave only worked when I debugging :) In master code missing _program_slave(...,...,...).
Thank you!!!
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BLmicro
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Re: 33CH MSI FIFO with DMA 2019/02/18 10:00:09 (permalink)
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I also have been trying to use MSI FIFOs and FIFOs with DMA lately and have seen similar issues. It appears some things don't work as described or maybe as you would expect.
 
My scenario is a 33CH128 used in an engine control application. The slave handles all input from sensors, the core engine control algorithm and all ADC of sensors. The master handles CAN messaging from the external Linux based touchscreen. The master holds configuration data in flash and sends it to the slave upon startup via MSI FIFOs. This works but I could not get it to work right with interrupts, just the FULL/EMPTY flags and polling. Polling is ok on startup but after the engine is running I now need to send metrics from the ADC data of about 15 sensors and more back to the Master to be forwarded to the touchscreen via CAN in real time. So now I need DMA.
 
My "dream" is to have the Master DMA read the metrics from the FIFO which would trigger the Slave DMA to write to the FIFO so the metrics data can flow unimpeded back to the touchscreen without any impact on engine operation. Sounds nice but I discovered a few things in prototyping this out in small steps.
 
It appears the FIFOs seem to work however the flags don't match the state of the FIFOs. A single write to the FIFO from the slave to the master causes the FIFO full flag to be set regardless of what RFITSEL is set to (I set it 0x11 because I want full to mean 32 words, but it doesn’t seem to matter).
 
Also I’m seeing the data ready interrupt (_MSIDTInterrup, master side) kick but it never clears after the FIFO is read out from slave to master (yes I clear _MSIDTIF in the ISR). So I have to poll during operation as opposed to using interrupts which is not preferable, ok for now but this needs to be revisited.
 
DMA on the Slave side seems to operate as expected, the DMA finishes and I get the interrupt stating such, however it doesn’t seem to put the data into the FIFO. It never appears on the Master side. The source is set as follows; DMADST0= &SWMRFDATA. So I can’t use DMA on the slave side, I have to send it from main, not cool but better than no metrics at all.
 
I have used Mailboxes in all sorts of ways (with the exception of mailboxes + DMA) and they work great, may incorporate that in the mean time as a work around.
 
Just wondering what other people have seen. Maybe some of this will go away with the CH512 which I am moving to soon.
 
-BL
 
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Weydert
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Re: 33CH MSI FIFO with DMA 2019/02/18 11:13:17 (permalink)
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Hi,
as I told some time ago: I had problem with DMA Overrun using the FIFO in the Master-Slave Interface.
Other people had DMA Overrun problem using ADC with FIFO.
I never used FIFOs on other devices before, all could be done with DMA instead. So my experience with FIFOs is ZERO.
But I think something is wrong with the implementation of the FIFOs in the CH series.

Mailboxes work well with DMA and as a bonus, the size of the transferred data-block can be greater than 32 words (max. words in FIFO).

My hint: forget FIFO, it is unlikly that you can solve the problem. Maybe in some month or years you will see the FIFO problem in an updated Errata.
 
Regards
Rainer
 
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BLmicro
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Re: 33CH MSI FIFO with DMA 2019/02/18 12:11:07 (permalink)
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Yes I think you are correct. I'm just going to have to implement a work around. I'm hoping maybe we can get even more confirmation.
 
None of the FIFO examples use INTERUPTS (they all poll) and none of the DMA examples use FIFOs. My application needs all three. Too good to be true I guess.
 
-BL
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