AnsweredHot!Setting a writable interrupt flag bit within ISR software code in PIC16F887

Author
ahmed11406
New Member
  • Total Posts : 8
  • Reward points : 0
  • Joined: 2018/09/07 16:50:24
  • Location: 0
  • Status: offline
2018/09/11 06:32:56 (permalink)
0

Setting a writable interrupt flag bit within ISR software code in PIC16F887

Hi, 
If an interrupt occurred, the memory pointer goes to Interrupt Vector memory location and then to the first instruction of the ISR code. the question is what will happen if inside ISR I set intentionally other writable (according to the datasheet) interrupt flag bit to High? 
that flag is set to high when a condition is met; to specify, when an iterator variable has reached certain value,  and both the flag and the variable will be cleared once that flag's interrupt routine gets fully executed.
  
Since nothing especial about ISR memory locations in terms of how CPU deals with them, I think that if a flag bit is set through ISR execution, the memory pointer will behave naturally no matter where the flag is set, and immediately (note the program doesn't continue executing the rest of ISR in this case) again goes to the Interrupt Vector location then to the start of the ISR locations and follow the conditions written there.
 
the second scenario is the program finishes executing ISR full code first then when it returns to the main program it checks if there's a flag is set and sparking ISR again accordingly. 
 
Of course in order for the interrupt to occur, all the Interrupt Enable Bit will be enabled for all cases regarded here.
 
Thanks in advance!
#1
qhb
Superb Member
  • Total Posts : 6838
  • Reward points : 0
  • Joined: 2016/06/05 14:55:32
  • Location: One step ahead...
  • Status: online
Re: Setting a writable interrupt flag bit within ISR software code in PIC16F887 2018/09/11 06:59:34 (permalink) ☼ Best Answerby ahmed11406 2018/09/11 09:58:19
+1 (1)
ahmed11406
If an interrupt occurred, the memory pointer goes to Interrupt Vector memory location and then to the first instruction of the ISR code.

Why do you list these as two items?
The "first instruction of the ISR code" is at the "interrupt vector memory location", so you're describing the same instruction in two different ways.
If you are silly enough to have a GOTO instruction at address 0004, get rid of it, and put your ISR code itself there.
 

the question is what will happen if inside ISR I set intentionally other writable (according to the datasheet) interrupt flag bit to High? 
that flag is set to high when a condition is met; to specify, when an iterator variable has reached certain value,  and both the flag and the variable will be cleared once that flag's interrupt routine gets fully executed.
  
Since nothing especial about ISR memory locations in terms of how CPU deals with them, I think that if a flag bit is set through ISR execution, the memory pointer will behave naturally no matter where the flag is set, and immediately (note the program doesn't continue executing the rest of ISR in this case) again goes to the Interrupt Vector location then to the start of the ISR locations and follow the conditions written there.

Wrong.
Nothing will happen until you exit the ISR, because the GIE flag is automatically cleared when you enter the ISR.
 

the second scenario is the program finishes executing ISR full code first then when it returns to the main program it checks if there's a flag is set and sparking ISR again accordingly.

Almost. It never gets back to the main code, because executing the RETFIE instruction sets GIE, so it will trigger the ISR again immediately.
 
post edited by qhb - 2018/09/11 07:00:39

Worst forum problems are now fixed, but the damn firewall is still there.
#2
1and0
Access is Denied
  • Total Posts : 8351
  • Reward points : 0
  • Joined: 2007/05/06 12:03:20
  • Location: Harry's Gray Matter
  • Status: offline
Re: Setting a writable interrupt flag bit within ISR software code in PIC16F887 2018/09/11 08:13:04 (permalink)
0
What are you trying to do?
 
 
#3
ahmed11406
New Member
  • Total Posts : 8
  • Reward points : 0
  • Joined: 2018/09/07 16:50:24
  • Location: 0
  • Status: offline
Re: Setting a writable interrupt flag bit within ISR software code in PIC16F887 2018/09/11 08:33:49 (permalink)
0
qhb
Nothing will happen until you exit the ISR, because the GIE flag is automatically cleared when you enter the ISR.

So, an interrupt module can't be initialized or disabled from the ISR code since its enable bit cannot be reached unless GIE is enabled, can it?
Thanks so much for your help. 
 
#4
ahmed11406
New Member
  • Total Posts : 8
  • Reward points : 0
  • Joined: 2018/09/07 16:50:24
  • Location: 0
  • Status: offline
Re: Setting a writable interrupt flag bit within ISR software code in PIC16F887 2018/09/11 08:41:32 (permalink)
0
1and0
What are you trying to do?

I want to fire an interrupt if a condition is meet. 
Consider a TMR0 increments a counter, then when that counter has reached a certain value after a calculated amount of time, the program fires another interrupt, clears TMR0 flag, disables TMR0 interrupt and zeroing the counter variable. This is performed inside TMR0 ISR.
post edited by ahmed11406 - 2018/09/11 08:42:50
#5
1and0
Access is Denied
  • Total Posts : 8351
  • Reward points : 0
  • Joined: 2007/05/06 12:03:20
  • Location: Harry's Gray Matter
  • Status: offline
Re: Setting a writable interrupt flag bit within ISR software code in PIC16F887 2018/09/11 08:59:35 (permalink)
+1 (1)
ahmed11406
 
I want to fire an interrupt if a condition is meet. 
Consider a TMR0 increments a counter, then when that counter has reached a certain value after a calculated amount of time, the program fires another interrupt, clears TMR0 flag, disables TMR0 interrupt and zeroing the counter variable. This is performed inside TMR0 ISR.

Then make the servicing of that other interrupt into a routine and call it from your Timer0 ISR. This same routine can also be called by its own ISR.
#6
pcbbc
Super Member
  • Total Posts : 453
  • Reward points : 0
  • Joined: 2014/03/27 07:04:41
  • Location: 0
  • Status: offline
Re: Setting a writable interrupt flag bit within ISR software code in PIC16F887 2018/09/11 09:27:47 (permalink) ☄ Helpfulby ahmed11406 2018/09/11 09:59:06
+1 (1)
I would say it is usually very bad practice to set an interrupt flag in code.  Having the flag set will usually cause the ISR code to assume some hardware actually requires servicing, for example an ADC complete or byte arrived on serial port, etc.  So the ISR will be preforming that action also, when no such event has actually occurred.
 
As 1and0 says, put your code into it's own function if it needs to be called from two places.
 
You can quite happily clear TMR0 flag and disable TMR0 from inside your TMR0 ISR code.  Indeed it is almost a 100% given that any interrupt handler should always clear it's own interrupt flag, otherwise there's a very real risk of locking up the CPU when it doesn't get cleared elsewhere due to some code path not being taken for some reason.
#7
ahmed11406
New Member
  • Total Posts : 8
  • Reward points : 0
  • Joined: 2018/09/07 16:50:24
  • Location: 0
  • Status: offline
Re: Setting a writable interrupt flag bit within ISR software code in PIC16F887 2018/09/11 09:51:34 (permalink)
0
How can I enable an TMR0 interrupt module into IOCB serving routine, while the datasheet says that GIE is disabled upon executing an service routine? can I re-enable it inside IOCB routine?   
#8
NKurzman
A Guy on the Net
  • Total Posts : 16304
  • Reward points : 0
  • Joined: 2008/01/16 19:33:48
  • Location: 0
  • Status: offline
Re: Setting a writable interrupt flag bit within ISR software code in PIC16F887 2018/09/11 09:52:53 (permalink)
+1 (1)
Your PIC has a single interrupt vector that handles all of the interrupt sources.
setting an interrupt flag will cause that interrupt to occur.  But since that PIC only has the one interrupt vector, it will not interrupt itself.  The flag will be handled in you interrupt code, Or if it is not will cause the Interrupt to re-enter as soon as it leaves. 
#9
NKurzman
A Guy on the Net
  • Total Posts : 16304
  • Reward points : 0
  • Joined: 2008/01/16 19:33:48
  • Location: 0
  • Status: offline
Re: Setting a writable interrupt flag bit within ISR software code in PIC16F887 2018/09/11 09:52:53 (permalink)
0
Your PIC has a single interrupt vector that handles all of the interrupt sources.
setting an interrupt flag will cause that interrupt to occur.  But since that PIC only has the one interrupt vector, it will not interrupt itself.  The flag will be handled in you interrupt code, Or if it is not will cause the Interrupt to re-enter as soon as it leaves. 
#10
qhb
Superb Member
  • Total Posts : 6838
  • Reward points : 0
  • Joined: 2016/06/05 14:55:32
  • Location: One step ahead...
  • Status: online
Re: Setting a writable interrupt flag bit within ISR software code in PIC16F887 2018/09/11 15:45:15 (permalink)
0
ahmed11406
qhb
Nothing will happen until you exit the ISR, because the GIE flag is automatically cleared when you enter the ISR.

So, an interrupt module can't be initialized or disabled from the ISR code since its enable bit cannot be reached unless GIE is enabled, can it?

Wrong again.
I never said anything like that.
When GIE is clear, it prevents a jump to the interrupt service routine, NOTHING ELSE.
As I already stated, if you have set an interrupt request flag, and the matching interrupt enable flag is also set, then the jump will occur as soon as GIE is set again by executing the RETFIE instruction.
 
ahmed11406
1and0
What are you trying to do?

I want to fire an interrupt if a condition is meet. 
Consider a TMR0 increments a counter, then when that counter has reached a certain value after a calculated amount of time, the program fires another interrupt, clears TMR0 flag, disables TMR0 interrupt and zeroing the counter variable. This is performed inside TMR0 ISR.

But this is all pointless. You are ALREADY inside the interrupt service routine. there is no need to set a hardware flag to get back there, you are already there.
As NKurzman just mentioned, you only have a single ISR that has to service all your interrupts. There is no separate "Timer ISR" or "USART ISR", they are all handled by one ISR.
So, as people have been trying to say, it's trivially easy to get the part of the ISR hjandling the timer to call the same code for this "other" interrupt.
 

Worst forum problems are now fixed, but the damn firewall is still there.
#11
Aussie Susan
Super Member
  • Total Posts : 3307
  • Reward points : 0
  • Joined: 2008/08/18 22:20:40
  • Location: Melbourne, Australia
  • Status: offline
Re: Setting a writable interrupt flag bit within ISR software code in PIC16F887 2018/09/11 20:36:39 (permalink)
+1 (1)
I think what the OP needs to realise is that there is a specific set of circumstances that will allow an ISR to be called. Firstly you need the GIE to be set - as the name suggests this is the 'global' interrupt enable bit and so is a way to make sure that *all* interrupts are enabled or disabled.
Secondly, you need the specific interrupt source's 'xxIE' (Interrupt Enable) bit to be set. If this bit is not set, then that interrupt source will not trigger the ISR.
Finally you need the interrupt source's "xxIF' (Interrupt Flag) bit to be set. This bit is normally set by the hardware to say that the ISR needs to be called, and cleared by the software to say that it has been serviced.
So all 3 bits have to be set for the ISR to be called.
You can set and clear the xxIE and xxIF bits anywhere. The GIE bit should not be played with at all except at the start to enable all interrupts to be services (and perhaps in some other very special circumstances when you *really* know what you are doing.)
The situation is similar if you are using one of the other MCUs that can have two (or perhaps more) ISRs but there are additional bits that are used to control the calling of a particular ISR.
(Slightly off the topic but, when you have an ISR that services several interrupts, you should test for both the xxIE and xxIF bits being set. IT is quite possible for the xxIF bit to be set but the xxIE bit to be cleared. This combination will not trigger the ISR but if something else does and all you are testing is the xxIF bit, then you can execute the associated code inappropriately.)
Susan
#12
qhb
Superb Member
  • Total Posts : 6838
  • Reward points : 0
  • Joined: 2016/06/05 14:55:32
  • Location: One step ahead...
  • Status: online
Re: Setting a writable interrupt flag bit within ISR software code in PIC16F887 2018/09/11 20:41:08 (permalink)
+1 (1)
Aussie Susan
(Slightly off the topic but, when you have an ISR that services several interrupts, you should test for both the xxIE and xxIF bits being set. IT is quite possible for the xxIF bit to be set but the xxIE bit to be cleared. This combination will not trigger the ISR but if something else does and all you are testing is the xxIF bit, then you can execute the associated code inappropriately.)

Agree in general, but only in the case where you ARE turning some IE bits off after initialisation.
If the bits are always set, then there's no need to test them.

Worst forum problems are now fixed, but the damn firewall is still there.
#13
Aussie Susan
Super Member
  • Total Posts : 3307
  • Reward points : 0
  • Joined: 2008/08/18 22:20:40
  • Location: Melbourne, Australia
  • Status: offline
Re: Setting a writable interrupt flag bit within ISR software code in PIC16F887 2018/09/12 19:38:57 (permalink)
+1 (1)
In post #5, the OP talks about disabling one of the interrupt sources which is why I mentioned this.
Susan
#14
1and0
Access is Denied
  • Total Posts : 8351
  • Reward points : 0
  • Joined: 2007/05/06 12:03:20
  • Location: Harry's Gray Matter
  • Status: offline
Re: Setting a writable interrupt flag bit within ISR software code in PIC16F887 2018/09/13 00:15:32 (permalink)
0
Aussie Susan
In post #5, the OP talks about disabling one of the interrupt sources which is why I mentioned this.

If it's the ONLY interrupt that will be disabled and it's not of high priority, place it as the last interrupt to check in the ISR and then there is no need to check its IE bit. ;)
 
#15
qhb
Superb Member
  • Total Posts : 6838
  • Reward points : 0
  • Joined: 2016/06/05 14:55:32
  • Location: One step ahead...
  • Status: online
Re: Setting a writable interrupt flag bit within ISR software code in PIC16F887 2018/09/13 00:51:40 (permalink)
0
That would still run it when it was disabled whenever any other interrupt was triggered.
(That's assuming you check every IE bit in every service. If you use "else if" to stop checking once you've found one that matches, then I guess your technique would work.)
If it is the only one that ever gets disabled, then it is the only one that needs an IE check alongside the IF check.
 

Worst forum problems are now fixed, but the damn firewall is still there.
#16
1and0
Access is Denied
  • Total Posts : 8351
  • Reward points : 0
  • Joined: 2007/05/06 12:03:20
  • Location: Harry's Gray Matter
  • Status: offline
Re: Setting a writable interrupt flag bit within ISR software code in PIC16F887 2018/09/13 00:59:13 (permalink)
0
qhb
... If you use "else if" to stop checking once you've found one that matches, then I guess your technique would work.

Correct.  All my interrupt handling (so far) are like that, instead of wasting time to check each and every interrupts that most likely are not triggered. ;)  Get in and out of the ISR as fast as possible; if there are pending interrupts, it will vector to the interrupt again.
 

If it is the only one that ever gets disabled, then it is the only one that needs an IE check alongside the IF check

... or do that.
 
post edited by 1and0 - 2018/09/13 01:09:57
#17
ahmed11406
New Member
  • Total Posts : 8
  • Reward points : 0
  • Joined: 2018/09/07 16:50:24
  • Location: 0
  • Status: offline
Re: Setting a writable interrupt flag bit within ISR software code in PIC16F887 2018/09/14 13:36:03 (permalink)
+1 (1)
Many thanks to all of you! it's really informative and helpful. 
#18
Jump to:
© 2018 APG vNext Commercial Version 4.5