Using MCP2517 with classic can bus (not FD)

void CAN2517_Init(void)
{
    uint8_t i = 0;
    APP_CANFDSPI_Init(CAN_1000K_4M);

    txObj.bF.ctrl.IDE = 0; // Extended CAN ID false
    txObj.bF.id.SID = 0x7df; // CAN ID

    txObj.bF.ctrl.BRS = 0; // Switch Bitrate true (switch to 2Mbps)
    txObj.bF.ctrl.FDF = 0; // CAN FD true
    txObj.bF.ctrl.DLC = 8; // Data length. 15 is 64 bytes

    for(i = 0;i <8;i++)
    {
      txd[i] = 0;
    }
}

void loop()
{

  txd[7] = can_msg_count >> 24;
  txd[6] = can_msg_count >> 16;
  txd[5] = can_msg_count >> 8;
  txd[4] = can_msg_count;

  can_msg_count++;

  APP_TransmitMessageQueue(); // Send out CAN FD frame

// if(digitalReadFast(int1_pin) == 0) // Read int1 pin on MCP2517FD
// {
// // It is low read out the data
// APP_ReceiveMessage_Tasks();
// }

// __delay_cycles(100);

}


void APP_CANFDSPI_Init(CAN_BITTIME_SETUP selectedBitTime)
{
    bool ramInitialized;
    txFromFlash = true;
    payload.On = false;

    ramInitialized = false;
    
    CAN_OSC_STATUS oscStat;

    DRV_SPI_Initialize();


    // Reset device
    DRV_CANFDSPI_Reset(DRV_CANFDSPI_INDEX_0);

    // Enable ECC and initialize RAM
// DRV_CANFDSPI_EccEnable(DRV_CANFDSPI_INDEX_0);

    if (!ramInitialized) {
        DRV_CANFDSPI_RamInit(DRV_CANFDSPI_INDEX_0, 0xff);
       ramInitialized = true;
    }

    // Configure device
    DRV_CANFDSPI_ConfigureObjectReset(&config);
    config.BitRateSwitchDisable = 1;
    config.IsoCrcEnable = 0;
    config.StoreInTEF = 0;

    DRV_CANFDSPI_Configure(DRV_CANFDSPI_INDEX_0, &config);

    // Setup TX FIFO
    DRV_CANFDSPI_TransmitChannelConfigureObjectReset(&txConfig);
    txConfig.FifoSize = 7;
    txConfig.PayLoadSize = CAN_PLSIZE_8;
    txConfig.TxPriority = 1;

    DRV_CANFDSPI_TransmitChannelConfigure(DRV_CANFDSPI_INDEX_0, APP_TX_FIFO, &txConfig);

    // Setup RX FIFO
// DRV_CANFDSPI_ReceiveChannelConfigureObjectReset(&rxConfig);
// rxConfig.FifoSize = 15;
// rxConfig.PayLoadSize = CAN_PLSIZE_8;

// DRV_CANFDSPI_ReceiveChannelConfigure(DRV_CANFDSPI_INDEX_0, APP_RX_FIFO, &rxConfig);
//
// // Setup RX Filter
// fObj.word = 0;
// fObj.bF.SID = 0xda;
// fObj.bF.EXIDE = 0;
// fObj.bF.EID = 0x00;

// DRV_CANFDSPI_FilterObjectConfigure(DRV_CANFDSPI_INDEX_0, CAN_FILTER0, &fObj.bF);
//
// // Setup RX Mask
// mObj.word = 0;
// mObj.bF.MSID = 0x0;
// mObj.bF.MIDE = 0; // Only allow standard IDs
// mObj.bF.MEID = 0x0;
// DRV_CANFDSPI_FilterMaskConfigure(DRV_CANFDSPI_INDEX_0, CAN_FILTER0, &mObj.bF);
//
// // Link FIFO and Filter
// DRV_CANFDSPI_FilterToFifoLink(DRV_CANFDSPI_INDEX_0, CAN_FILTER0, APP_RX_FIFO, true);

    // Setup Bit Time
    DRV_CANFDSPI_BitTimeConfigure(DRV_CANFDSPI_INDEX_0, (CAN_BITTIME_SETUP) selectedBitTime, CAN_SSP_MODE_AUTO, CAN_SYSCLK_40M);
 // DRV_CANFDSPI_BitTimeConfigure(DRV_CANFDSPI_INDEX_0, selectedBitTime, CAN_SSP_MODE_AUTO, CAN_SYSCLK_20M);
    
    // Setup Transmit and Receive Interrupts
// DRV_CANFDSPI_GpioModeConfigure(DRV_CANFDSPI_INDEX_0, GPIO_MODE_INT, GPIO_MODE_INT);
// DRV_CANFDSPI_TransmitChannelEventEnable(DRV_CANFDSPI_INDEX_0, APP_TX_FIFO, CAN_TX_FIFO_NOT_FULL_EVENT);
// DRV_CANFDSPI_ReceiveChannelEventEnable(DRV_CANFDSPI_INDEX_0, APP_RX_FIFO, CAN_RX_FIFO_NOT_EMPTY_EVENT);

// DRV_CANFDSPI_ModuleEventEnable(DRV_CANFDSPI_INDEX_0, CAN_TX_EVENT | CAN_RX_EVENT);

    DRV_CANFDSPI_OscillatorStatusGet(DRV_CANFDSPI_INDEX_0, &oscStat);

    // Select Normal Mode
    DRV_CANFDSPI_OperationModeSelect(DRV_CANFDSPI_INDEX_0, CAN_CLASSIC_MODE);

}