AnsweredHot!CCP module in Compare mode toggles output on Fosc/4 regardless of chosen clock source

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cchalm
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2018/08/21 19:09:41 (permalink)
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CCP module in Compare mode toggles output on Fosc/4 regardless of chosen clock source

Hey all. I'm using a CCP module in Compare mode, where the output toggles on match. It uses a timer clocked by an external 40kHz signal. The instruction clock (Fosc/4) is 8MHz. All of the documentation I've found suggests that this should work fine. In practice, though, the output oscillates for the entire duration of the CCP timer clock cycle that produced the match, and then ends in an arbitrary state. The oscillation frequency is half of Fosc/4, suggesting that the toggling logic is clocked from Fosc/4 regardless of the timer chosen for the module.
 
Did I miss something, or is this undocumented behavior?
 
I attached a program that reproduces the behavior. Compiled with xc8 2.00 for pic16f18877. And here's a capture of the output behavior. Yellow is the clock signal for the timer the CCP module uses, and purple is the CCP module output.
 

 
Thanks!
 
 
 
For reference:
 
The datasheet (pic16f18877) says on page 437:
 
In order for Compare mode to recognize the trigger event on the CCPx pin, TImer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source.
 
I also launched MCC to see if it could tell me anything about this setup, and it produced this warning:
 
Configure Timer 1 to operate on frequency equal to or lesser than FOSC/4 to use it as Compare source.
 
That seems fine as well; the timer is clocked at 40kHz and Fosc/4 is 8MHz.
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davekw7x
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Re: CCP module in Compare mode toggles output on Fosc/4 regardless of chosen clock source 2018/08/21 22:41:23 (permalink)
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cchalm
 
Did I miss something...



Ignore the MCC warning.  It's irrelevant, if slightly annoying. (See Footnote.)
 
Now...
I'm assuming that you set up Timer 1 as a synchronized counter, since that's what the Data Sheet says to do.

And I'm assuming that you set the CCP1 mode to 0b0001 (Toggle CCP output and reset Timer1).

Well here's the deal...
When Timer 1 reaches a count value equal to the contents of CCPRH and CCPRL a reset signal is issued to Timer 1. But (and this is a Big But), since Timer 1 is synchronized, it doesn't get reset until the next TCK1 rising edge.  For that time (i.e. a complete cycle of TCK1 input) the CCP1 comparator matches TMR1 and the output toggles every Fosc/2 period  (Output is toggling at 8 MHz, which generates a  4 MHz square wave during that time, right?)
 
[Edit]
Upon reflection, I think it has nothing to do with operating in synchronized mode.  Here's what makes it act that way, according to the Data Sheet:

Note: In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge after any one or
more of the following conditions:
.
• Firmware writes to TMR1H or TMR1L

In other words (I think) after writing to TMRH or TMR1L it must wait until the next rising edge of its clock to take effect.  Presumably this applies to the "reset" signal from the CCP.  At least that's consistent with what we observe with this CCP mode.
[/Edit]

Bottom line: I don't think the compare mode is useful if you are expecting the CCP1 output to toggle exactly once every time Timer 1 reaches the specified value.

A suggestion: Don't use the CCP output (i.e. don't map it to a pin).  Enable the CCP interrupt and in the CCP ISR toggle a GPIO output pin.  (It works for me for my PIC16F18857---only one interrupt is generated for each match.)
 
That might give some insight into the operation of the CCP module, but if you are going to do something that requires program intervention, you could just use Timer 2, 4,  or 6 to generate a periodic interrupt and have its ISR toggle the output pin.
 
Due to the nature of interrupt-driven output, there will be a little jitter in the output for either of these two methods.  Of course, since the input clock is (presumably) asynchronous with respect to the system clock, the output will necessarily have some jitter, so I don't think the interrupt stuff will add significantly, but I don't know what your actual requirements are.

On the other hand, a cleaner approach, not requiring interrupt or other program intervention, might be to consider using a CLC/NCO combination to do the deed if you haven't already used the required resources for other things.  (I think that might work, but I haven't tested it.)  Note that the NCO output itself may be jittery (that is the nature of this type of signal genaration), so, depending on your requirements, that might not be more suitable than the interrupt/toggle approach of the previous paragraphs.  Maybe it's worth a shot...


Regards,

Dave
Footnote:
I have started using MCC in certain evaluation projects.  Sometimes it seems like a shortcut to initialization.
I mean, MCC can sometimes help us get things set up, but I, personally, can not say that I ever attained "insight" from the use of MCC.
post edited by davekw7x - 2018/08/21 23:39:29

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cchalm
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Re: CCP module in Compare mode toggles output on Fosc/4 regardless of chosen clock source 2018/08/22 00:24:07 (permalink)
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Thanks for the information Dave.
 
davekw7x
Bottom line: I don't think the compare mode is useful if you are expecting the CCP1 output to toggle exactly once every time Timer 1 reaches the specified value.


Darn, I'll look into other options then. I implemented a hack to work around this problem using a CLC module, maybe I can expand that into something elegant.
 
One point of clarification: I am using CCP mode 0b0010, which toggles the output but does not reset the timer. I originally tried the reset-timer mode, but I ran into exactly the problems you describe. Instead, I add to the CCPR value in the handler for each match and allow the timer to continue counting. That approach makes more sense anyway because I'm timing a series of adjacent pulses.
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Re: CCP module in Compare mode toggles output on Fosc/4 regardless of chosen clock source 2018/09/11 10:16:00 (permalink) ☼ Best Answerby cchalm 2018/09/11 22:46:02
+3 (3)
What you are seeing is likely related to errata 4.1.  Check the revision of your part.  It should be fixed in rev A3.

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davekw7x
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Re: CCP module in Compare mode toggles output on Fosc/4 regardless of chosen clock source 2018/09/11 17:44:57 (permalink)
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coffee critic
What you are seeing is likely related to errata 4.1.

I agree; now that you point it out (thank you very much) I think it is a definite possibility even though our "error" condition is not exactly the same as described.
 
coffee critic
 Check the revision of your part.  It should be fixed in rev A3.

Maybe or maybe not.  The problem is that even if it gets fixed with the next one, there is, in general, no way to guarantee that you can order a particular chip revision.  In any case, in the meanwhile I need to work with what I have (Rev A2 as it happens).
 
However, the workaround in the errata works nicely to get a square wave that is divided down from an external Timer clock with no run-time overhead, assuming that one of the CLC modules is otherwise unused.  I wish I had thought of that.  (And maybe next time I will pay closer attention to the errata.).
 
Here's the procedure I followed to get a 1 kHz square wave from a 40 kHz external clock with no software intervention.
  1. In the "Easy Setup" window configure the CCP1 module for "Pulseartmr" compare mode
  2. In the CCP1 "Registers" window set CCPR1H:CCPR1L to a value equal to
      TimerFrequency / (2 * OutputFrequency) - 1

      So, for 40 kHz timer clock and 1 kHz output frequency,:
        CCPR1H = 0;
        CCPR1L = 19
  3. Set up a CLC as a D-flipflop
        Connect the Clock input to CCP1 Output
        Connect the D input to Inverted(CLC1 Output)
  4. Assign the CLC output signal to an appropriate output pin.
  5. Taa-daa!
 
Tested on my PIC16F18857.
 
Note that if you assign a PPS pin to the CCP1 output you can see a train of pulses that are one T1CLK period in duration, repeated every 2 milliseconds.  The D-Flipflop divides the pulse train down into a 1 kHz square wave.
 
Regards,
 
Dave



post edited by davekw7x - 2018/09/11 19:05:24

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cchalm
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Re: CCP module in Compare mode toggles output on Fosc/4 regardless of chosen clock source 2018/09/11 22:45:54 (permalink)
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Thanks coffee critic. I wasn't aware of erratas at all, so I learned something today! And it seems reasonable to assume that the issue mentioned in the errata extends to my use case.
 
Unfortunately the issue makes the CCP module no more useful to me than a plain old timer with an adjustable period and pulse-on-postscaler-match. I was hoping to use the built-in toggle functionality to save a CLC and eventually downsize to a pic16f1619 or 1615 (which have the same issue).
 
Nonetheless, mystery solved!
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coffee critic
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Re: CCP module in Compare mode toggles output on Fosc/4 regardless of chosen clock source 2018/09/12 10:15:57 (permalink)
+1 (1)
Talk to your sales rep, FAE or field sales engineer.  They can order a specific revision for you to prototype.  Later you can have them set you up with a custom part that will limit your order to A3 or newer.  Most distis (or Microchip Direct) can fulfill these custom parts. 

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qhb
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Re: CCP module in Compare mode toggles output on Fosc/4 regardless of chosen clock source 2018/09/12 13:18:04 (permalink)
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coffee critic
Talk to your sales rep, FAE or field sales engineer.  They can order a specific revision for you to prototype.  Later you can have them set you up with a custom part that will limit your order to A3 or newer.  Most distis (or Microchip Direct) can fulfill these custom parts.

That sounds very useful.
Is there an MOQ (minimum order quantity) though?
 
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coffee critic
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Re: CCP module in Compare mode toggles output on Fosc/4 regardless of chosen clock source 2018/09/12 16:09:59 (permalink)
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Either a setup charge or a MOQ.  FYI I have never had much luck with Thief River Falls... ordering custom part numbers.  Everything else is great however.   

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