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Helpful Reply[solved] DDR SCL failed

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marelcom
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2018/07/26 02:16:03 (permalink)
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[solved] DDR SCL failed

Hi
 
I developt my Application on the StarterKit PIC32MZ2064DAG169 with MEBII
The Application runs fine.

Now I started to adapt this application to our target with a PIC32MZ2025DAG176
It seems that on this PIC32 the DDRSCL is not working or fails all the time. Then after startup the Application is hanging in this function "DDR_PHY_Calib(void)" in file sys_memory_ddr_static. There is a while loop which calls the function "PLIB_DDR_PHY_SCLStatus" This function returns always false.
DDRSCLCFG0 = 0x01004057
DDRSCLCFG0 = 0x00000401
DDRSCLCFG0 = 0x00000000
DDRSCLLAT = 0x00000043
 
DDRVREF is set to 1.8V external

So is there a bug in DDR or how can I fix this issiue

MPLABX = v4.20
Harmony = v2.06
Debuger = Real ICE

Thanks & regards
Markus
post edited by marelcom - 2018/07/27 22:56:18
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marelcom
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Re: DDR SCL failed 2018/07/27 22:24:45 (permalink)
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Finally we could solve this issue.
Pin DDRVREF must be connect to 0.9V. This can be generated out of a voltage diveder built out of two 1kohm resistors. High of voltage devider is connect with 1.8V which is used to feed the VDDR1V8 pins.

In the silicon Version A1, the internal DDRVREF generator does not work so you must connect DDRVREF to external 0.9V. This is written in PIC32MZ Errata sheet
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ecdhe
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Re: [solved] DDR SCL failed 2018/08/09 09:57:40 (permalink)
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marelcom
Then after startup the Application is hanging in this function "DDR_PHY_Calib(void)" in file sys_memory_ddr_static. There is a while loop which calls the function "PLIB_DDR_PHY_SCLStatus" This function returns always false.



I had the same symptom, but my solution was different.  My design already supplied the proper 0.9vdc bias to the DDRVREF pin.
 
In my case, the Memory PLL (MPLL) target frequency was set to 400MHz per the Harmony v2.06 default.  I noticed that the harmony example "write_read_ddr2" sets the MPLL value to only 200MHz.  When I lowered the MPLL value in my project to 200MHz, my application was finally able to proceed. 
 
Further experimentation showed that 250MHz also worked, but 300MHz did not.  This lines up with the data sheet specs for the DDR2 timing requirements; despinte the DDR2 controller being able to support 400MHz outputs from the MPLL, the DDR2 timing requirements show the Clock Frequency (tCK) for the DDR2 iteself listed at 5ns typical(200MHz) with no min and max listed.  
 
 
I'm using the PIC32MZ2064DAG169 Rev A1 with 32MB internal DDR2.  MPLabX 5.00, XC32 v2.05, Harmony v2.06.
 
 
update: spec sheet details
 
post edited by ecdhe - 2018/08/09 10:18:32
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rmorley78
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Re: [solved] DDR SCL failed 2018/10/14 20:10:26 (permalink)
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ecdhe,
 
Did you every find a solution to the internal DDR running at half speed? I am a having the same issue on a custom board. The DDR will not initialize when the DDR clock is set to 400MHz, but will work at 200MHz. I've have compared my setup to the example found in harmony and the only difference was the ODT setting for writes and the DDR type was set to internal which was not what the example had(Micron MT47H64M16). I believe that it may be the timing parameters are not set right. 
 
If you have solved the problem could you please post your solution.
 
Thanks. 
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ecdhe
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Re: [solved] DDR SCL failed 2018/10/29 12:12:42 (permalink) ☄ Helpfulby cjohnson 2018/10/31 10:58:14
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rmorley78Did you every find a solution to the internal DDR running at half speed?

 
In my case, the internal DDR is not running at "half speed"; the internal DDR in the PIC32MZ2064DA169 is only capable of being clocked at at a nominal 200MHz or, from my testing, a little above.
 
Unfortunately, the Harmony 2.06 BSP that Microchip supplies for the "PIC32MZ DA Starter Kit w/Internal DDR" defaults the MPLL to 400MHz -- a value at which the DDR can never operate.  This is something Microchip would have caught if they'd ever tried to use their own BSP for a DDR-based project.
 
Setting the MPLL to the internal DDR's actual top speed of 200MHz caused the internal DDR to work for me.  All the other DDR settings were left as Harmony's defaults.
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cjohnson
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Re: [solved] DDR SCL failed 2018/10/31 10:59:21 (permalink)
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On top of the default project always being 400 MHz, every time you open the "Auto Calculate" button for the MPLL, it defaults to 400 MHz.

Colby Johnson
Product Design Engineer
OEM Solutions, Inc.
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