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AnsweredHot!PIC24FJ.. Memory organization

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RamNadler
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2018/06/27 00:58:50 (permalink)
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PIC24FJ.. Memory organization

I am getting confused with the program memory addresses of the 16 bit microcontrollers.
For example, for a 64KByte memory I expect to find 65,536 bytes of 8 bits.
Since the micro is 16 bit, I expect that the final address will be (65,536/2 - 2) = 0x7FFE
But according to the data sheet (page 42 of PIC24FJ64GA70X) the final address is 00AFFEh
 
Can some one please explain this?
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BobAGI
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Re: PIC24FJ.. Memory organization 2018/07/02 05:34:25 (permalink)
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The PIC24 uses 24 bit instruction words (hence the name PIC24).
This means that each instruction occupies 3 bytes, but in the flash memory the addressing is on 32 bit chunks with the high byte (called phantom byte) being disregarded.

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qɥb
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Re: PIC24FJ.. Memory organization 2018/07/02 05:48:05 (permalink)
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Many people have problems understanding that the register width and the opcode width are different.
Von Neumann architecture is so prevalent that Harvard Architecture is a mystery to most.

This forum is mis-configured so it only works correctly if you access it via https protocol.
The Microchip website links to it using http protocol. Will they ever catch on?
PicForum "it just works"
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flubydust
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Re: PIC24FJ.. Memory organization 2018/07/02 06:25:05 (permalink)
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PIC24 FLASH memory is 24 bits wide. The high order byte can not be accessed directly. The two low order bytes can  so each needs an address. PIC24 FLASH address space is 2/3rds the size of FLASH in bytes.
 
The PIC24 program counter is always even (the 0 bit doesn't actually exist) so it always points at the low byte of a 24 bit FLASH word.

 
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1and0
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Re: PIC24FJ.. Memory organization 2018/07/02 12:02:41 (permalink) ☼ Best Answerby RamNadler 2018/07/02 12:41:38
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Each PIC24 instruction is 24-bit wide represented as two 16-bit words, where the upper byte of the upper word is a phantom byte. Each of these words get an address; i.e. lower word an even address and upper word an odd address.
 
Your PIC device has user flash program memory with addresses 0x0000-0xAEFE and flash config words with addresses 0xAF00-0xAFFE (0xAF00-0xAF2C are implemented on yours). This is 0xB000 (or 45056) words or 90112 bytes. Remember 1/4 of these bytes are phantom bytes. So 90112 * 3/4 = 67584 bytes which is approximately 64 Kbytes.
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RamNadler
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Re: PIC24FJ.. Memory organization 2018/07/02 12:50:13 (permalink)
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1and0
...67584 bytes which is approximately 64 Kbytes.



Thanks.
I was afraid that the word "approximately" will appear.
In the same data sheet I see that the 128KB device has 704 write blocks and the 256KB device has 1376 write blocks.
256 is 128X2 but 1376 is not 704X2.
So I understand now that address calculations according to the flash size is not linear as I expected it to be.
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1and0
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Re: PIC24FJ.. Memory organization 2018/07/02 12:56:44 (permalink)
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RamNadler
I was afraid that the word "approximately" will appear.
In the same data sheet I see that the 128KB device has 704 write blocks and the 256KB device has 1376 write blocks.
256 is 128X2 but 1376 is not 704X2.
So I understand now that address calculations according to the flash size is not linear as I expected it to be.

Each PIC24 instruction is three bytes wide. You cannot divide 64KB, 128KB, and 256KB by three evenly.
 
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flubydust
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Re: PIC24FJ.. Memory organization 2018/07/02 18:43:38 (permalink)
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1and0
Each PIC24 instruction is 24-bit wide represented as two 16-bit words, where the upper byte of the upper word is a phantom byte. Each of these words get an address; i.e. lower word an even address and upper word an odd address.



That is wrong. The FLASH memory is byte addressable. The low byte at even addresses the middle byte at odd addresses and the high byte has no address and is not accessible (the low byte address is also used to accesses the whole 24 bit word for instructions and table operations). The only 'phantom' bytes are in 32 bit hex files for the devices.

 
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1and0
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Re: PIC24FJ.. Memory organization 2018/07/02 21:36:11 (permalink)
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flubydust
That is wrong. The FLASH memory is byte addressable. The low byte at even addresses the middle byte at odd addresses and the high byte has no address and is not accessible (the low byte address is also used to accesses the whole 24 bit word for instructions and table operations). The only 'phantom' bytes are in 32 bit hex files for the devices.

From the PIC24 Family Reference Manual:
 

Attached Image(s)

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flubydust
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Re: PIC24FJ.. Memory organization 2018/07/03 04:16:42 (permalink)
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The manual is garbage.
The least significant word can be accessed directly as a word with even address or as separate bytes with even and odd addresses.
 
The most significant word can only be accessed via table operations using an even address for the whole 24bit word.
 

 
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T Yorky
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Re: PIC24FJ.. Memory organization 2018/07/03 05:59:49 (permalink)
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@flubydust,
'That is wrong. The FLASH memory is byte addressable. The low byte at even addresses the middle byte at odd addresses and the high byte has no address and is not accessible'
I think you may be getting PSV mode mixed up with general principles. What you have described are applicable when accessing in PSV using the RAM/FLASH access mode. But all Flash is accessible using the TBLRDL/H instructions. These instructions allow access to the full 24bits (plus phantom byte). Only the even addresses are valid. An address with an odd value actually references the previous even address. This is explained in the manual. The High or Low Word within the 24 bits (32 with phantom) is selected by using the L or H suffix.
AND just to complicate matters, the later PIC24 'flavours' with EDS give full access to all 24 bits using standard instructions. Just need to select the correct page. This goes for the latest 1024kB versions which have page after page after page !!!
Hope this assists.
T Yorky
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flubydust
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Re: PIC24FJ.. Memory organization 2018/07/03 08:02:31 (permalink)
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T Yorky
I think you may be getting PSV mode mixed up with general principles.



The general principle is that a 24 bit wide memory has one address for each 24 bit word. The only reason the program counter has a notional bit 0 and we are drivelling on about odd and even addresses is to support byte addressing of the low order 16 bits in the PSV window.
 
Full access to all 24 bits using standard instructions is news to me. What new/updated instruction does that and how when the high order word doesn't have an address?

 
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T Yorky
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Re: PIC24FJ.. Memory organization 2018/07/03 09:05:31 (permalink)
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Going off topic a bit here..
(Some of) The later FJs have enhancements. Can address 16M of external RAM (! only 16Mhz cpu !). The PSV becomes effectively the EDS window. The whole Flash is paged into the EDS allowing access to it all. Lower word, upper word, each byte of lower or upper word. Whatever you want. The bit 0 does have a use...!
I had to update a encrypted bootloader last year to accomodate this new 'flavour' of PIC. It is a significant change for FJs. Like a FJ/EP mongrel.
All FJs have had access to all 24 bits using the standard TBL instructions.
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1and0
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Re: PIC24FJ.. Memory organization 2018/07/03 12:26:26 (permalink)
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flubydust
 
The general principle is that a 24 bit wide memory has one address for each 24 bit word. 

I understand your point of view on the addressing, where the lower byte of the lower word at even address, the upper byte of the lower word at odd address, and the upper word has no address.
 
A different view is that of the manual written from an organization perspective, in that every word gets an "address" in sequential order. As you've said each 24-bit instruction has one address, that is word-aligned on the lower word (i.e. bit 0 is always 0). Here, bit 0 is used to address not only the lower and upper bytes of the lower word, but also the lower and upper bytes of the upper word (even though this upper byte does not exist -- read returns 0x00 and write has no effect). In other words, in Byte mode bit 0 determines which byte in the upper or lower program memory word is accessed.
 
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flubydust
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Re: PIC24FJ.. Memory organization 2018/07/03 12:30:48 (permalink)
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T YorkyThe whole Flash is paged into the EDS allowing access to it all. Lower word, upper word, each byte of lower or upper word. Whatever you want. The bit 0 does have a use...!



So I read the GA6/GB6 series datasheet and see the enhancement is using the most significant bit of the page register to select which word of program memory is mapped into PSV space. Kinda useless having to change the page register every time you need to switch between reading the first two bytes and 3rd byte. Bit 0 doesn't come into it. Effectively they have doubled the program memory address space and the top half is full of high order and phantom bytes.

 
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Gort2015
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Re: PIC24FJ.. Memory organization 2018/07/03 14:54:36 (permalink)
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The addresses are 16 bit, it's just that each 16bit address holds 24 bits.
 
table rd/wr high accesses bits 23:16
 
;----------------------------------------------------
KeyWords:
.pascii "PS",<0>        ;serial prescaler
.pascii "T",<0>,<0>  ;wait time between operations and E time
.pascii "SPI"              ;serial module 1-4
.pascii "SER"             ;serial module 1-4
.pascii "SDO"            ;serial date out
.pascii "SCK"             ;serial clock
.pascii "CS",<0>       ;chip select
.pascii "RS",<0>       ;register select
.pascii "RW",<0>      ;not read/write
.pascii "E",<0>,<0> ;enable trigger
.pascii "BUS"            ;4/8bit bus
.pascii <0>
;----------------------------------------------------

 
;----------------------------------------------------
.equ table,        w1
.equ lowword,        w2
.equ highword,        w3
.equ tmp,        w4
.equ setptr,        w5
.equ STRING,        w6    ;global
.equ index,        w7

_parser:
    mov        STRING,LineBuffer_src+VAR_CPYSTRING
    mov        #tblpage(KeyWords),tmp
    mov        tmp,TBLPAG
    mov        #tbloffset(KeyWords),table
    clr        highword                ;4th
    ;~~~~~~~~~~~~~~~~~~~~~~~~~~~
looptbl:
    mov        #WREG2,setptr
    tblrdh.b [table],tmp        ;3rd
    tblrdl.b [table++],[setptr++]   ;1st
    tblrdl.b [table++],[setptr++]   ;2nd
    mov.b   tmp,[setptr++]        ;3rd
    ;~~~~~~~~~~~~~~~~~~~~~~~~~~~
    cp0.b   lowword
    bra        z,notfoundname
    mov        #WREG2,setptr
    ;~~~~~~~~~~~~~~~~~~~~~~~~~~~
loopname:
    mov.b   [setptr],tmp
    cp0.b   tmp
    bra        z,checkterm
    cp.b    tmp,[STRING]
    bra        nz,nexttable
    ;~~~~~~~~~~~~~~~~~~~~~~~~~~~
    inc        STRING,STRING
    inc        setptr,setptr
    bra        loopname
    ;~~~~~~~~~~~~~~~~~~~~~~~~~~~
nexttable:
    mov        LineBuffer_src+VAR_CPYSTRING,STRING
    bra        looptbl
    ;~~~~~~~~~~~~~~~~~~~~~~~~~~~
    etc...


MPLab X playing up, bug in your code? Nevermind, Star Trek:Discovery will be with us soon.
https://www.youtube.com/watch?v=Iu1qa8N2ID0
+ ST:Continues, "What Ships are Made for", Q's back.
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flubydust
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Re: PIC24FJ.. Memory organization 2018/07/03 15:24:46 (permalink)
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1and0A different view is that of the manual written from an organization perspective, in that every word gets an "address" in sequential order.



But it isn't organised that way and there is no concept of using 16bit word addresses. Word selection is done by L and H table operation opcodes. The manual is garbage, it is as dumb as saying from an organization perspective program memory is addressed as 2 x 12 bit words.

 
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T Yorky
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Re: PIC24FJ.. Memory organization 2018/07/03 16:32:26 (permalink)
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Below is an extract from the PIC manual...
'In Byte mode, the source address depends on the contents of Ws. If Ws is
not word-aligned, zero is stored to the destination register (due to
non-existent program memory). If Ws is word-aligned, the third program
memory byte (PM<23:16>) at the specified program memory address is
stored to the destination register.'
..and as above, with the revised FJ, there is a direct mapping between the address (inc bit 0) and the EDS page to access the Flash..
sorry can't really assist any more on the subject..
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1and0
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Re: PIC24FJ.. Memory organization 2018/07/03 21:22:05 (permalink)
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Here's Microchip description of the 16-bit PIC MCU Program Memory and Extended Data Space of mapping program memory.
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T Yorky
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Re: PIC24FJ.. Memory organization 2018/07/04 03:40:09 (permalink) ☄ Helpfulby RamNadler 2018/07/04 07:14:03
4.5 (2)
@RamNadler,
Just note the 64K, 128K, 256K (eg PIC24FJ64.., PIC24FJ128.., PIC256K) are guidance values in some cases !!! Some devices do not contain exactly the 2^n bytes. For example some PIC EP 256K devices have more than 256K, nearer 280K (inc vectors).
Alternative to calc shown above..
Search for the Memory Organisation in the data sheet. This will show the Flash memory map. If the last Flash address is 0x2ABFE (for example) then add 2 = 0x2AC00 (allows for address 0).
Divide by 2 for the number of PIC24 instructions = 0x15600.
Then multiply by 3 for the 3 bytes per instruction = 0x40200.
Then divide by 0x400 (1Kbyte) = 256.5 K
This is just over 256K.
 
T Yorky
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