Hot!Input Capture and Output Compare clocking from wrong source

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Whozaa
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2018/06/14 06:56:15 (permalink)
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Input Capture and Output Compare clocking from wrong source

I am trying to use the Input Capture module in a pic24f16ka304 to measure the frequency of a series of pulses. I am also trying to use the Output Compare modules as "extra" timers. I plan to ignore the actual output pin, and just use the interrupt.
 
The problem I'm having is that both of these modules refuse to clock from other timers. They will only clock from the internal cycle clock. If I understand the datasheet (and reference manuals) correctly, you should be able to use the ICTSEL bits (for the Input Capture) and the OCTSEL bits (for the Output Compare) and pick which clock source you want to use. But no matter what I select, the modules always increment at 62.5nS (the internal cycle clock).
 
I've tried using different timers, different compare/capture modules, but nothing seems to make a difference. I have also checked the errata for this chip, and I don't see anything that would apply here.
 
I've attached my "macros.inc" file. I've already verified with the watch window that my macros work, but I figured I'd include them so that you can run this code if you want.
 
 ;------------------------------------------------------------------------------
 ; Processor Setup
 ;------------------------------------------------------------------------------
 .include "p24F16KA304.inc"
 .include "macros.inc"
 .list
 

 config __FOSCSEL,FNOSC_FRCPLL
 config __FOSC,OSCIOFNC_OFF & FCKSM_CSDCMD
 config __FWDT,FWDTEN_OFF
 config __FICD,ICS_PGx2

 .global __reset

 
 
 
.bss
 placeholder: .space 2

 




.text

;RESET VECTOR -----------------------------------------------------------------------------
 __reset:
 
  BTSS OSCCON, #LOCK ;wait for the PLL to lock
 BRA $-2
 
 CLR CLKDIV ;set frc postscaler to make a 32Mhz Fosc, 16Mhz Fcy, 62.5nS Tcy
 
 ;Stack Pointer Init ---
 MOV #__SP_init,W15 ; Initalize the Stack Pointer
 MOV #__SPLIM_init,W0 ; Initialize the Stack Pointer Limit Register
 MOV W0,SPLIM ; (__SP_init & __SPLIM_init values are calculated by linker)
 NOP ; Add NOP to follow SPLIM initialization
  


;PORT INITIALIZE -------------------------------------------------------------------------------------

 
 CLR ANSA ;make all PORTA analog inputs digital
 BCLR TRISC, #RC8 ;make the output compare pin an output

;------------------------------------------------------------------------------------------------------
 



;OUTPUT COMPARE INITIALIZE -----------------------------------------------------------------------------------------

 CLR T1CON
 MOV #16, W0 ;setup timer to interrupt every 1uS
 MOV W0, PR1

 CLR OC2R ;set OC period to 100uS
 MOV #100, W0
 MOV W0, OC2RS
 mOCTSEL OC2CON1, #0b100 ;use TMR1 for clock source
 mSYNCSEL OC2CON2, #0b11111 ;self sync
 mOCM OC2CON1, #0b101 ;turn module on
 
 BSET T1CON, #TON

;----------------------------------------------------------------------------------------------------------





;INPUT CAPTURE AND TIMERS INITIALIZE -----------------------------------------------------------------------------

;TIMER2 (IC1 time base) TMR2 rolls over every 50uS
 MOV #800, W0
 MOV W0, PR2

;IC1
 MOV #0x0460, W0 ;run from Timer2, interrupt every 4th capture
 MOV W0, IC1CON1
 MOV #0x0000, W0 ;free run
 MOV W0, IC1CON2
 MOV #0x0003, W0 ;turn on module, capture every rising edge
 IOR IC1CON1

 BSET T2CON, #TON ;turn on the time base


;-------------------------------------------------------------------------------------------------------------------







 main:


 BRA $
 



.end

post edited by Whozaa - 2018/06/14 07:00:00
#1

3 Replies Related Threads

    Whozaa
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    Re: Input Capture and Output Compare clocking from wrong source 2018/06/19 13:02:49 (permalink)
    3 (1)
    I think I figured it out. I thought you could use the timer as a programmable time base by setting its PRx register to whatever you wanted and that the IC/OC modules would increment when the timer hit the PRx value.
     
    But it seems the IC and OC modules do not clock from the timer interrupt/overflow, they clock from the timer's clock source. If I set the timer's prescaler to some value other than 1:1, then the IC/OC modules increment at the prescaled rate.
     
    Hmmm... that's not nearly as flexible as I'd thought originally.
    #2
    qɥb
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    Re: Input Capture and Output Compare clocking from wrong source 2018/06/19 13:12:57 (permalink)
    4 (1)
    I think you're misunderstanding what these modules do.
    They don't have their own counter, they latch or compare the current value of the timer register itself.
     

    This forum is mis-configured so it only works correctly if you access it via https protocol.
    The Microchip website links to it using http protocol. Will they ever catch on?
    PicForum "it just works"
    #3
    Whozaa
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    Re: Input Capture and Output Compare clocking from wrong source 2018/06/20 07:00:14 (permalink)
    3 (1)
    This pic family uses the "Input Capture with Dedicated Timer" peripheral which has its own timer register. When you look at the control register ICxCON1 in the datasheet and/or hardware reference manual, you can use the ICTSEL bits to select the clock source. The choices are system clock, timer1, timer2, timer3, etc. I thought if you picked one of those timers, the IC module would increment whenever that timer overflowed/reset. Sort of like having a 16bit prescaler.
     
    But I found out that's not how it works.
     
    I can see this behavior being useful if you were trying to clock the IC or OC modules from an external source. You could run the external clock source through one of the timer modules and then set the IC/OC module to use that timer. But that doesn't help me for this project.
     
    Thank you for taking the time to reply. I will reconsider my coding strategy for this project and see if I can still use this pic family. I have a dspic33FJ64GP206 that I may try as well, although it seems like overkill to use a dsp just for the capture/compare modules.
    #4
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