Hot!Driving capacitive loads

Page: 12 > Showing page 1 of 2
Author
paul.b_iow
New Member
  • Total Posts : 8
  • Reward points : 0
  • Joined: 2017/07/21 08:33:31
  • Location: 0
  • Status: offline
2018/05/14 02:45:00 (permalink)
0

Driving capacitive loads

There were some threads a few years  back about driving capacitive loads, but I still don't think the situation is clear.
Normally to keep device stresses within acceptable limits the peak current (perhaps a few hundred ns or less at low duty ratio) can be higher than the mean current. The spec we have for PIC outputs just gives a single value. It would be good to get limits better characterised.
I have a circuit layed out on PCB with a pin used as ADC input with 10nF capacitor to ground. Now as an afterthought it would be useful to be able to configure the pin as an output during test and set the pin high, which means charging the 10nF through 5 V.
This would only happen once in the life of the chip at 25C. Clearly the current would be higher than the pin 50mA limit for a few hundred ns (probably about 100mA peak) chip is 16f18854.
The supply pin currents would be below their max limits, so I don't think it would cause a problem with the chip operation.
For a typical MOSFET in isolation The peak current could easily exceed the mean rating by this ratio.
If the circuit was not fixed in stone this would not be a problem.
Does anyone know if this is likely to cause a problem.
Many thanks Paul
 
 
#1

23 Replies Related Threads

    PStechPaul
    Super Member
    • Total Posts : 2042
    • Reward points : 0
    • Joined: 2006/06/27 16:11:32
    • Location: Cockeysville, MD, USA
    • Status: offline
    Re: Driving capacitive loads 2018/05/14 13:02:29 (permalink)
    +2 (2)
    You may be able to figure the maximum current by using the typical output pin high voltage and current. For a PIC16F15325, the output drops to Vdd-0.7V a 6 mA, which is about 117 ohms. Thus, short circuit current at 5 VDC supply would be about 43 mA, which is below the 50 mA maximum. The TC of 117 ohms and 10 nF is only about 1 uSec, so I think you are safe. To be even more certain, you could activate the weak pull-up for a little while to charge the capacitor before turning on the high output.

     
    #2
    Mysil
    Super Member
    • Total Posts : 2885
    • Reward points : 0
    • Joined: 2012/07/01 04:19:50
    • Location: Norway
    • Status: offline
    Re: Driving capacitive loads 2018/05/14 14:41:23 (permalink)
    +1 (1)
    Hi,
    There are differences between devices, but I agree that figures by PStechPaul probably are typical.
    Apart from absolute maximum values, specifications concentrate more of what current and capacitance
    may be tolerated with rated signal levels and signal frequency.
     
    For some devices there are characteristics diagram of output voltage at different currents.
    There are significant internal resistance Rdson in output transistors, typically higher in the High-side switch,
    than in the Low-side output driver.
    It is my impression that many PIC devices are practically short-circuit proof when sourcing current thru the High-side transistor. At least as long as only single pins are loaded.
    Some devices have much lower resistance when sinking current thru Low-side switch.
     
    If you really want to drive Capacitive load, you may use a MOSFET driver , as used for Power MOSFET and IGBT transistors in power inverter circuits.
     
       Mysil
    #3
    paul.b_iow
    New Member
    • Total Posts : 8
    • Reward points : 0
    • Joined: 2017/07/21 08:33:31
    • Location: 0
    • Status: offline
    Re: Driving capacitive loads 2018/05/15 01:16:47 (permalink)
    0
    Thankyou both for your replies. I think what you both say sounds correct. I think I had not made it clear, I have already worked out the max current which is the ~ 100mA I mentioned ( the chip limit is 50mA), and the time constant is about 500ns, so it will only be above the limit for around 250ns. Unfortunately I can't precherge it because there is a R to ground. By design I would not get into this position, but the HW design is fixed.
    My feeling was that this would be OK but some threads in the past have come to the conclusion that the limit must never be exceeded for any instant of time. This is only required to happen once in lifetime. I will at some point do a much more severe test to make sure no measurable difference has happened to the chip.
    I think it would be helpful to people if you could characterise this a bit bettter Microchip. are you listening ?
    I expect a 50/50 squarewave at max sink and source current and max frequency may stress the chip more than charging a 1nF capacitor every once minute (which is outside the spec limits).
    Thanks all Paul
    #4
    jack@kksound
    code tags!
    • Total Posts : 2762
    • Reward points : 0
    • Joined: 2014/05/14 10:03:19
    • Location: 0
    • Status: offline
    Re: Driving capacitive loads 2018/05/15 10:51:16 (permalink)
    0
    If the concern for the overcurrent draw is heat accumulation in the chip you could reduce this possibly by charging the cap with pulses rather then a constant ON state of the output. Maybe increase the duty cycle of the charging pulses as the cap charges to reduce overall charge time. Just a thought...
    #5
    crosland
    Super Member
    • Total Posts : 1257
    • Reward points : 0
    • Joined: 2005/05/10 10:55:05
    • Location: Bucks, UK
    • Status: offline
    Re: Driving capacitive loads 2018/05/15 11:55:30 (permalink)
    +1 (1)
    paul.b_iowsome threads in the past have come to the conclusion that the limit must never be exceeded for any instant of time.

     
    That would be an idiotic position to take. All loads are capacitive. There will always be transients, no matter how short or difficult to detect.
    #6
    PStechPaul
    Super Member
    • Total Posts : 2042
    • Reward points : 0
    • Joined: 2006/06/27 16:11:32
    • Location: Cockeysville, MD, USA
    • Status: offline
    Re: Driving capacitive loads 2018/05/15 12:36:00 (permalink)
    +1 (1)
    What is needed is an I^2t rating, which determines the instantaneous power and heating. For a PIC, this would mostly comprise the output MOSFETs, but also the wire bonds to the chip, and whatever "fuses" are involved as a result of configuration settings and pin-to-peripheral mapping.

     
    #7
    paul.b_iow
    New Member
    • Total Posts : 8
    • Reward points : 0
    • Joined: 2017/07/21 08:33:31
    • Location: 0
    • Status: offline
    Re: Driving capacitive loads 2018/05/16 01:49:10 (permalink)
    0
     
    Yes there needs to be better Microchip data on ratings. These are two quotes from two different "super members" in the past:
    "  "That 25 mA is an absolute maximum rating. For design purposes, think "Drawing or sourcing 25.000001 mA for 1 femtosecond will destroy the IC.".   ""
    "   "The IO pins are rated at a maximum of 25ma regardless of the duty cycle.  If you are neededing peak currents higher than this you must buffer them. "   "
     
    I can see from a point of view of the stresses in the chip this is not a logical way to specify the max. stress. But from what microchip give in datasheets it is the only formal interpretation.
    I understand your point  crossland but how else can we interpret the datasheets. I would not say it is idotic but just very formal. We need to be given the limits so we don't have to guess them.
    As you say crossland it is not very practical: assuming there is not a series resistor right by the output pin, the track Zo must be inconveniently high to limit the current to 25 mA .
    A micro is a bit more complicated than a simple FET in terms of rating; could a surge cause other problems such as causing the Vdd to fall (actually on the silicon) and trip the brown out. This is why we need it from the manufacturer.
    #8
    crosland
    Super Member
    • Total Posts : 1257
    • Reward points : 0
    • Joined: 2005/05/10 10:55:05
    • Location: Bucks, UK
    • Status: offline
    Re: Driving capacitive loads 2018/05/16 04:28:57 (permalink)
    +1 (1)
    Please do me the courtesy of getting my name right. It's right there in front of you.
     
    Very few datasheets give anything other than recommended (i.e. normal long term operation) and absolute maximums. The abs. max. rating are always couched in ifs, buts and maybes. There clearly isn't a 25mA fuse in every I/O. Even a traditionl fuse works well beyond its rating, depending, as pointed out, on I^2T.
    Navigate to the sdk/lib folder of the SDK and execute the following two commands:
    $ objcopy --redefine-sym SSLeay=SSLeay@OPENSSL_1.0.1 libserverlib.a

    $ objcopy --redefine-sym SSLeay=SSLeay@OPENSSL_1.0.1 libserverlibd.a


    #9
    paul.b_iow
    New Member
    • Total Posts : 8
    • Reward points : 0
    • Joined: 2017/07/21 08:33:31
    • Location: 0
    • Status: offline
    Re: Driving capacitive loads 2018/05/16 05:58:38 (permalink)
    0
    Sincere apologies about the name crosland, my mistake.
    Power devices usually have detailed spec. on current limits not just a single value.
    #10
    Zero Magnitude
    New Member
    • Total Posts : 2
    • Reward points : 0
    • Joined: 2018/05/14 15:54:30
    • Location: 0
    • Status: offline
    Re: Driving capacitive loads 2018/05/16 08:54:22 (permalink)
    +1 (1)
    All ratings are statistical likelyhoods, not absolute values.  i.e. 25mA means "most of the chips in this line will handle 25mA most of the time."  not "25.00001 = instant fail".  You might get that one chip that can handle 30mA just fine on the prototype but in production they'll start failing randomly.  
     
    Same as with write cycles.  There's not a counter, just at some point that's probably near 100k or 200k, it's going to stop working properly.    
    #11
    JorgeF
    Super Member
    • Total Posts : 3287
    • Reward points : 0
    • Joined: 2011/07/09 11:56:58
    • Location: PT/EU @ Third rock from the Sun
    • Status: offline
    Re: Driving capacitive loads 2018/05/16 12:35:57 (permalink)
    +1 (1)
    Hi
    paul.b_iow
    Power devices usually have detailed spec. on current limits not just a single value.

    For some odd reason I fail to see a microcontrolers or its i/o pins as a "power devices".
     
    Best regards
    Jorge
     
    #12
    Mysil
    Super Member
    • Total Posts : 2885
    • Reward points : 0
    • Joined: 2012/07/01 04:19:50
    • Location: Norway
    • Status: offline
    Re: Driving capacitive loads 2018/05/16 15:04:18 (permalink)
    0
    Even then, there are some aspects of "power" driving directly from Microcontroller I/O pins.
    Think about controlling high intensity LED devices,
    driving gate of power MOSFET transistor,
    or I2C clock  line with 400 pF capacitance at 400 kHz continously.
     
    Specification limits of + and - 50 mA for PIC16F188xx devices is already higher than previous generation devices.
    Also Clamp current + and - 20 mA is higher than many devices.
    PIC16F18854 seem to have quite powerful output cells.
    Diagram 38-1  in Datasheet DS40001826B-page 593,
    show current up to -45 mA while maintaing output voltage 3 V.
    Interesting, that when temperature increase, output voltage and current is reduced.
    Figure 38-2 show output voltage when sinking current up to 100 mA, this is outside of continous current specification limit.
     
    For a microcontroller, specification of power drive capability is even more complicated than for a single switching transistor. Any PIC have I/O cells densely packed around the edge of the chip.
    It would be possible to create a pulse drive diagram, or energy spec for a single I/O pin, similar to what is done for switch transistors.
    But then questions come up:
    What if 2 adjacent pins are driven at the same time?
    What if all 8 pins in a register are driven?
    What if 2 pins with their output cells located on Opposite corners of the chip?
     
    Anyway, specifications must be valid for a chip that is already at max specification temperature,
    or there must also be derating specifications. It just get more complicated.
    There is no simple answer to the original question.
     
       Mysil
    #13
    crosland
    Super Member
    • Total Posts : 1257
    • Reward points : 0
    • Joined: 2005/05/10 10:55:05
    • Location: Bucks, UK
    • Status: offline
    Re: Driving capacitive loads 2018/05/17 05:17:58 (permalink)
    0
    For some devices Microchip specify a max. per port as well as max. per pin.
     
    They also specify the max through power pins which does not allow for all pins to be driven to max. at the same time.
    #14
    Mysil
    Super Member
    • Total Posts : 2885
    • Reward points : 0
    • Joined: 2012/07/01 04:19:50
    • Location: Norway
    • Status: offline
    Re: Driving capacitive loads 2018/05/17 08:02:08 (permalink)
    +1 (1)
    Hi,
    Diagram in datasheet, Figure 38-2 seem to indicate internal resistance RDSon in the range 15 to 20 Ohm,
    for the Low-side switch when device is powered by 5 V.
    Similar Figure 38-1, when sourcing current thru High-side transistor, RDSon 45 to 60 Ohm.
    This is lower internal resistance than previous generations of devices.
     
    This device  PIC16F18854, and family,  have Slew Rate control for all Output pins,
    controlled by SLRCONx register for each pin individually.
    Activating Slewrate control could reduce transient current to within specification limit for steady-state current.
    I am not quite convinced that it will change the energy dissipation in the output stage any much.
     
       Mysil
    #15
    paul.b_iow
    New Member
    • Total Posts : 8
    • Reward points : 0
    • Joined: 2017/07/21 08:33:31
    • Location: 0
    • Status: offline
    Re: Driving capacitive loads 2018/05/22 03:59:18 (permalink)
    +1 (1)
    Thanks Mysil, that is a very good point about SLR, I have done the code now and on other things, but that is a setting I should have used. I could not see on the datasheet any indication of what the slew rate was though, must look into it. Sorry delay had been busy doing other things and not looked at this. When a capacitor charges through a resistive path the energy stored is equal to the energy dissipated, so slew rate will not effect the chip dissipation, but that is not the concern.
     
    Paul
    #16
    jack@kksound
    code tags!
    • Total Posts : 2762
    • Reward points : 0
    • Joined: 2014/05/14 10:03:19
    • Location: 0
    • Status: offline
    Re: Driving capacitive loads 2018/05/22 09:57:29 (permalink)
    +1 (1)
    When a capacitor charges through a resistive path the energy stored is equal to the energy dissipated, so slew rate will not effect the chip dissipation, but that is not the concern.

    I don't think so, the "energy" stored in the capacitor will flow through the resistance of the drivers on the chip, resulting in heat in those drivers. The slower the charge rate the more time allowed for the dissipation of this heat from the chip substrate and hence a lower rise in chip temperature. Slew rate definitely affects overall chip temperature however it may or may not be significant in a particular application.
    #17
    Mysil
    Super Member
    • Total Posts : 2885
    • Reward points : 0
    • Joined: 2012/07/01 04:19:50
    • Location: Norway
    • Status: offline
    Re: Driving capacitive loads 2018/05/22 10:56:55 (permalink)
    0
    Hi, Jack
    Just what Paul pointed out in message #16.
    When a Capacitor is charged thru a resistor, when equilibrium is reached, then equal amounts of energy have been dissipated in the in the resistor, that is silicon of the chip, as have been stored into the capacitor.
    So when activating slew rate control, energy dissipated is not changed, only distribution in time and space.
     
    I do not know precisely how output drivers and slew rate are arranged in the chip.
    I have some idea, that to achieve lower RDSon, that silicon area for output transistors have been increased, possibly by parallelling multiple cells. Then comes the question how slew-rate limitation is achieved, possibly by reducing the number of active cells, or using some resistive or current control elements, so the volume of silicon that is involved may be different, and possibly smaller.
    Anyway, peak current have been reduced, which was the original question.
     
       Mysil
    post edited by Mysil - 2018/05/22 13:45:22
    #18
    jack@kksound
    code tags!
    • Total Posts : 2762
    • Reward points : 0
    • Joined: 2014/05/14 10:03:19
    • Location: 0
    • Status: offline
    Re: Driving capacitive loads 2018/05/22 11:46:08 (permalink)
    0
    Mysil,
     
    Of course, very good insight. My concern was overall chip heating which may be the real culprit in potential damage from over-current draw due to capacitor charging. By pulsing or reducing the slope of the charge some reduction in overall chip temp is achieved (As you say the heat generated is distributed over a longer time period) and this MAY reduce potential damage (or maybe not!).
    #19
    paul.b_iow
    New Member
    • Total Posts : 8
    • Reward points : 0
    • Joined: 2017/07/21 08:33:31
    • Location: 0
    • Status: offline
    Re: Driving capacitive loads 2018/05/23 01:47:12 (permalink)
    -1 (1)
    In fact it does not matter if the capacitor is charged linearly, in any other rise time function; provided the capacitor is fully charged and then fully discharged in a repetitive switching function, and the charging is lossy (i.e. no inductors) then the dissipation in the resistive charge / discharge device is independant of how fast it is charged / discharged.
    Dissipation and average chip temp rise only depends on the voltage and capacitor value.
    As mysil pointed out the stress on the chip may be changed by how it is done.
    #20
    Page: 12 > Showing page 1 of 2
    Jump to:
    © 2018 APG vNext Commercial Version 4.5