Hot!I/O behaviour during power ramp

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Foxie
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2018/03/20 12:01:37 (permalink)
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I/O behaviour during power ramp

I plan to use the PIC18F27K40.
 
As far as I understand, whenever the chip is in reset the I/O will be high impedance.
 
However, what happens during the initial power-up ramp? Do the I/O pins remain high impedance all the way from 0 to Vbor (2.7V), and remain high impedance until code execution begins? I plan to enable the power up reset timer and brown out reset.
 
Likewise, what happens when the supply ramps down below the brown out reset threshold? Will all I/O be forced high impedance and remain that way down to 0V?
 
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I also have a second unrelated question about the I/O pins.
 
Do the pin modes (open drain, TTL / CMOS select) also apply when a peripheral has control over the pin? I would like to freely choose either CMOS or TTL for the UART receive, and use an open drain output for the UART transmit.
 
#1

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    Jams100001
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    Re: I/O behaviour during power ramp 2018/10/25 14:57:56 (permalink)
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    Foxie
    However, what happens during the initial power-up ramp? Do the I/O pins remain high impedance all the way from 0 to Vbor (2.7V), and remain high impedance until code execution begins? I plan to enable the power up reset timer and brown out reset.

    Foxie,
    First off the reset section of the datasheet talks about all of this.  As a quick start any reset puts the part in high impedance mode.  The pins options are not selected until code execution starts.  Code execution doesn't start unit all of the POR BOR and oscillator selections are met. once a stable oscillator is established then code execution begins.
    Jams100001
    Foxie
    Likewise, what happens when the supply ramps down below the brown out reset threshold? Will all I/O be forced high impedance and remain that way down to 0V?
     

    Foxie,
    When the Brown out threshold has been breeched the parts resets. enabling the flag to designate a brown out reset occured. Any reset forces all the I/O's to their reset state which is in the datasheet.
    Jams100001
    Foxie
    Do the pin modes (open drain, TTL / CMOS select) also apply when a peripheral has control over the pin? I would like to freely choose either CMOS or TTL for the UART receive, and use an open drain output for the UART transmit.

    Foxie,
    I believe the peripherals have priority over the pins normal operation. I would just say be careful switching pin operation to make sure the pins will do what you want them to.
    Jams100001
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    crosland
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    Re: I/O behaviour during power ramp 2018/10/26 01:11:17 (permalink)
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    You should also consider the speed of the Vdd rise/fall time and whether it is monotonic.
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    RISC
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    Re: I/O behaviour during power ramp 2018/10/27 03:14:01 (permalink)
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    Hi,
    Outside the specification, you can only make guesses...and you cannot (fully) rely on your observations because the behaviour is not garanteed.
    If the MCLR is held low the internal initialization of the PIC probably also depends upon the internal clock start-up.
    I "imagine" that it is not an asynchronous design internally and therefore "things" will start to change internally when the clock starts to have significant amplitude .
    Regards
     
    #4
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