I/O behaviour during power ramp
I plan to use the PIC18F27K40.
As far as I understand, whenever the chip is in reset the I/O will be high impedance.
However, what happens during the initial power-up ramp? Do the I/O pins remain high impedance all the way from 0 to Vbor (2.7V), and remain high impedance until code execution begins? I plan to enable the power up reset timer and brown out reset.
Likewise, what happens when the supply ramps down below the brown out reset threshold? Will all I/O be forced high impedance and remain that way down to 0V?
I also have a second unrelated question about the I/O pins.
Do the pin modes (open drain, TTL / CMOS select) also apply when a peripheral has control over the pin? I would like to freely choose either CMOS or TTL for the UART receive, and use an open drain output for the UART transmit.