hmmm, i tried , 2, 4, 6 and 255 AD clocks cycles but it seemed the same. Though I have tried it again just now, and it seems to make some difference. How do I arrive at the correct acq time?

There is a 64MHz micro clock, the AD clock is Fosc/128, so 500,000 MHz, which is 2uS. There are 32 samples being taken in a loop, so there is a sample being taken every 2uS. The first 32 sample conversion is separated from the second by about 20mS, and the third and subsequent 32 sample conversions are 40mS apart.

So, I thought that 2 AD clock cycles would be sufficient.

This is the code I am using

while(ADCNT < ADRPT) //ADRPT = 32

{

value = ADCC_GetSingleConversion(channel);

}

ADACLR=1;

adc_result_t ADCC_GetSingleConversion(adcc_channel_t channel)

{

// select the A/D channel

ADPCH = channel;

// Turn on the ADC module

ADCON0bits.ADON = 1;

//Disable the continuous mode.

ADCON0bits.ADCONT = 0;

// Start the conversion

ADCON0bits.ADGO = 1;

// Wait for the conversion to finish

while (ADCON0bits.ADGO)

{

}

// Conversion finished, return the result

return ((ADFLTRH << 8) + ADFLTRL);

}

post edited by brownt - 2018/02/13 06:20:29