Hot!PIC32MZ Internal Flash

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tahoe
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2018/02/07 13:00:20 (permalink)
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PIC32MZ Internal Flash

Hello,

I am try to clarify the process for writing to the internal flash per documentation. 

"Row Word programming will only succeed if the target address is in a page that is not write-protected. Once a row is programmed, it must be erased before any word in it can be programmed again, even if changing a bit from an erased ‘1’ state to a ‘0’ state."

So, how I read this is as such. I can write to that row once then if I wanna write to it again I have to erase an entire page as a page is the minimum erase operation. Am I reading that correctly? That would mean I have keep track of an entire page so I don't erase currently program data. 

Also, so I don't stall out the CPU when I write to internal flash what is the proper way to write the opposite bank?
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    Larry.Standage
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    Re: PIC32MZ Internal Flash 2018/02/08 10:25:37 (permalink)
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    Yes, you are correct that a page has to be erased before any row can be programmed. It's part of the nature of flash memory that erasing takes place on large chunks.
     
    The CPU does not stall as long as it is either a) running from the cache, or b) running from some memory other than the one you're trying to erase/program. In the case of flash, you can run out of 1/2 of the program memory while programming the other half. If you're running out of RAM, you can program any flash memory.
    #2
    tahoe
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    Re: PIC32MZ Internal Flash 2018/02/12 11:51:48 (permalink)
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    Larry,
     
    Thank you for your quick response.  I am going to design my firmware just to write pages. 
     
    #3
    Mr.Mxyzptlk2620
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    Re: PIC32MZ Internal Flash 2018/02/13 08:53:09 (permalink)
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    Tahoe, Larry,
    I have also read that quote about only writing to a row once before erasing the whole page. I beg to differ.
     
    My experience with the PIC32MZ is that you can write to the same row more than once, provided that you only change bits from ones to zeroes in that row, and provided that you only write to the same row once between power cycles.
     
    I habitually invalidate rows by writing all zeroes to them even if the rows have been written to before (once in a previous power cycle). I do this whenever I want to flush my NVM mirror situated in RAM to NVM. The previous incarnation in NVM is invalidated and new rows are written to. If no more free rows (with all data bits set) are available, I start erasing pages. Always after writing to rows and/or erasing pages, I reset the processor.
     
    Another point I want to bring up is that the harmony v2.05 NVM driver (in drv_nvm.c) is not actually capable of writing rows. I have verified this by repeatedly writing a pattern to a row (after erasing its page) and reading the row back again. The check always fails, not only in one position but all over. None of the DMA components have been turned on yet (I do the testing inside the SYS_Initialize function, calling the DRV_NVM_Tasks procedure in between NVM calls in order to be able to get the result of the operations) so that is not the problem.
     
    Test code (I break in the emulator after each read to check the result):
     
    #define TEST_NVM
    #ifdef TEST_NVM
    unsigned char globalWriteNVMBuffer[DRV_NVM_ROW_SIZE];
    unsigned char globalReadNVMBuffer[DRV_NVM_ROW_SIZE];
    #endif
    void SYS_Initialize ( void* data )
    {
    ..
    ..
    sysObj.drvNvm = DRV_NVM_Initialize(DRV_NVM_INDEX_0, (SYS_MODULE_INIT *)&drvNvmInit);
    sysObj.drvSDCard = DRV_SDCARD_Initialize(DRV_SDCARD_INDEX_0,(SYS_MODULE_INIT *)&drvSDCardInit);

    #ifdef TEST_NVM
    DRV_NVM_COMMAND_HANDLE commandHandle;
    DRV_HANDLE driverHandle = DRV_NVM_Open(DRV_NVM_INDEX_0, DRV_IO_INTENT_EXCLUSIVE | DRV_IO_INTENT_READWRITE);
    DRV_NVM_Erase(driverHandle, &commandHandle, 0, 1);
    while (DRV_NVM_COMMAND_COMPLETED != DRV_NVM_CommandStatus(driverHandle, commandHandle))
    {
    DRV_NVM_Tasks(sysObj.drvNvm);
    }
    DRV_NVM_Read(driverHandle, &commandHandle, globalReadNVMBuffer, 0, sizeof(globalReadNVMBuffer));
     
    // All bits in the page are set now
     
    int i;
    for (i = 0; i < sizeof(globalWriteNVMBuffer); i++)
    {
    globalWriteNVMBuffer = i & 0xff;
    }
    DRV_NVM_Write(driverHandle, &commandHandle, globalWriteNVMBuffer, 0, 1);
    while (DRV_NVM_COMMAND_COMPLETED != DRV_NVM_CommandStatus(driverHandle, commandHandle))
    {
    DRV_NVM_Tasks(sysObj.drvNvm);
    }
    DRV_NVM_Read(driverHandle, &commandHandle, globalReadNVMBuffer, 0, sizeof(globalReadNVMBuffer));
     
    // The row in globalReadNVMBuffer is vastly different from the one in globalWriteNVMBuffer

    #endif
     
    ..
    ..
    }
     
     
     
    The good news is that I have modified the NVM driver so that it uses the Quad Word approach (128 bits) with 4 internal 32 bit data registers instead of using the source address register. This works perfectly. From the outside, the application interface to the NVM driver is kept untouched: Entire rows are being written per call to DRV_NVM_Write, but inside the driver the number of rows is translated to number of 128 bit blocks during the operation (for the PIC32MZ2048EFM124 one row write - 2 KBytes - is translated into 128 Quad writes).
    #4
    NKurzman
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    Re: PIC32MZ Internal Flash 2018/02/13 10:42:07 (permalink)
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    The issue here may be related to PIC32s (and PIC24s) that have ECC. It may not be possible to do partial writes due the ECC.  For Non ECC Flash it is possible to write many times for a single erase. as long as it is a one to zero transition.
    #5
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