• AVR Freaks

Hot!PIC18f26k40 SPI code

Author
gharesh4
New Member
  • Total Posts : 9
  • Reward points : 0
  • Joined: 2018/01/26 23:14:39
  • Location: 0
  • Status: offline
2018/02/07 03:23:50 (permalink)
0

PIC18f26k40 SPI code

I have tried the following code with PIC18F26K40 SPI,
 
#pragma config FEXTOSC = XT // External Oscillator mode Selection bits (XT (crystal oscillator) above 100 kHz, below 8 MHz; PFM set to medium power)
#pragma config RSTOSC = LFINTOSC// Power-up default value for COSC bits (Low-Frequency Oscillator)
// CONFIG1H
#pragma config CLKOUTEN = OFF // Clock Out Enable bit (CLKOUT function is disabled)
#pragma config CSWEN = ON // Clock Switch Enable bit (Writing to NOSC and NDIV is allowed)
#pragma config FCMEN = ON // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor enabled)
// CONFIG2L
#pragma config MCLRE = EXTMCLR // Master Clear Enable bit (If LVP = 0, MCLR pin is MCLR; If LVP = 1, RE3 pin function is MCLR )
#pragma config PWRTE = OFF // Power-up Timer Enable bit (Power up timer disabled)
#pragma config LPBOREN = OFF // Low-power BOR enable bit (ULPBOR disabled)
#pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled , SBOREN bit is ignored)
// CONFIG2H
#pragma config BORV = VBOR_2P45 // Brown Out Reset Voltage selection bits (Brown-out Reset Voltage (VBOR) set to 2.45V)
#pragma config ZCD = OFF // ZCD Disable bit (ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON)
#pragma config PPS1WAY = ON // PPSLOCK bit One-Way Set Enable bit (PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle)
#pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config DEBUG = OFF // Debugger Enable bit (Background debugger disabled)
#pragma config XINST = OFF // Extended Instruction Set Enable bit (Extended Instruction Set and Indexed Addressing Mode disabled)
// CONFIG3L
#pragma config WDTCPS = WDTCPS_31// WDT Period Select bits (Divider ratio 1:65536; software control of WDTPS)
#pragma config WDTE = OFF // WDT operating mode (WDT Disabled)
// CONFIG3H
#pragma config WDTCWS = WDTCWS_7// WDT Window Select bits (window always open (100%); software control; keyed access not required)
#pragma config WDTCCS = SC // WDT input clock selector (Software Control)
// CONFIG4L
#pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-003FFFh) not write-protected)
#pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (004000-007FFFh) not write-protected)
#pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (008000-00BFFFh) not write-protected)
#pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (00C000-00FFFFh) not write-protected)
// CONFIG4H
#pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-30000Bh) not write-protected)
#pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
#pragma config SCANE = ON // Scanner Enable bit (Scanner module is available for use, SCANMD bit can control the module)
#pragma config LVP = OFF // Low Voltage Programming Enable bit (HV on MCLR/VPP must be used for programming)
// CONFIG5L
#pragma config CP = OFF // UserNVM Program Memory Code Protection bit (UserNVM code protection disabled)
#pragma config CPD = OFF // DataNVM Memory Code Protection bit (DataNVM code protection disabled)
// CONFIG5H
// CONFIG6L
#pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-003FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (004000-007FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks)
// CONFIG6H
#pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)
 
 
void SPI_Init_Master() {
/*PORT definition for SPI pins*/
TRISAbits.TRISA2 = 1; /* RB0 as input(SDI) */
TRISAbits.TRISA4 = 0; /* RB1 as output(SCK) */
TRISAbits.TRISA5 = 0; /* RA5 as a output(SS') */
TRISAbits.TRISA3 = 0; /* RC7 as output(SDO) */
TRISAbits.TRISA1 = 0; /* RA1 Output */
/*to initialize SPI Communication configure following Register*/
CS = 1;
SSP1STAT = 0x40; /*Data change on rising edge of clk , BF=0*/
SSP1CON1 = 0x22; /*master mode,Serial enable, idle state low for clk, fosc/64 */
PIR3bits.SSP1IF = 0;
/* disable the ADC channel which are on for multiplexed pin when used as an input */
ADCON0 = 0; /*this is for de-multiplexed the SCL and SDI from analog pins*/
ADCON1 = 0x0F; /*this makes all pins as a digital I/O pins*/
}
 
void SPI_Write(signed char x) {
CS = 0;
unsigned char data_flush;
SSP1BUF = x; /* put data in SSBUF which has to transmit */
while (!PIR3bits.SSP1IF); /* wait for complete 1 byte transmission */
PIR3bits.SSP1IF = 0; /* clear SSPIF flag */
data_flush = SSP1BUF; /* flush the data as simultaneous read occurs */
CS = 1;
}
 
unsigned char SPI_Read()
{
SSP1BUF = 0xff; /* Put flush data in SSBUF to read from device */
while (!PIR3bits.SSP1IF); /* wait for complete 1 byte transmission */
PIR3bits.SSP1IF = 0;
return (SSP1BUF); /* read data as it is returned from slave to master.
so SSPBUF is ready to receive new data.*/
}
#1

2 Replies Related Threads

    m_alizd
    Starting Member
    • Total Posts : 36
    • Reward points : 0
    • Joined: 2016/02/28 02:21:37
    • Location: 0
    • Status: offline
    Re: PIC18f26k40 SPI code 2021/01/27 20:02:50 (permalink)
    0
    Did it work?
    What was your query?
    #2
    ric
    Super Member
    • Total Posts : 29861
    • Reward points : 0
    • Joined: 2003/11/07 12:41:26
    • Location: Australia, Melbourne
    • Status: online
    Re: PIC18f26k40 SPI code 2021/01/27 20:14:38 (permalink)
    +2 (2)
    I hope he's not still hanging on for an answer after three years...
     

    I also post at: PicForum
    Links to useful PIC information: http://picforum.ric323.co...opic.php?f=59&t=15
    NEW USERS: Posting images, links and code - workaround for restrictions.
    To get a useful answer, always state which PIC you are using!
    #3
    Jump to:
    © 2021 APG vNext Commercial Version 4.5