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AnsweredPIC24F32KA304: _TRISA9 _NOT_ high impedance input at reset???

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SirCut
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2018/01/07 13:32:33 (permalink)
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PIC24F32KA304: _TRISA9 _NOT_ high impedance input at reset???

Hello my friends,
 
I designed a layout assuming that the PIC24F32KA304 TRISA9 pin was set to 1 (input, hi-z) for all resets. 
 
However, after having observed reset problems (power consumption) with my design, I now read the datasheet reset state for TRISA9 as 0 (output)!! This might explain the problems that I am observing.
 
This seems unconventional/unusual. I just wanted to check with the forum. Can you experienced folks on this forum confirm that the datasheet and, more importantly, the actual behaviour of the hardware for pin RA9 at all resets is, in fact to set pin as OUTPUT and NOT as input?
I read this in Table 4-12 of the datasheet in the "TRISA" row.
 
Thanks for any help
 
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qɥb
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Re: PIC24F32KA304: _TRISA9 _NOT_ high impedance input at reset??? 2018/01/07 13:39:51 (permalink) ☼ Best Answerby SirCut 2018/01/08 20:55:20
5 (1)
I suspect it's a typo in the datasheet, and should be "0FDF", not "00DF".
You could check yourself in only a couple of minutes. Just load any code in debug mode with a PK3 or ICD3, stop on the first instruction, and inspect TRISA yourself.
 

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SirCut
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Re: PIC24F32KA304: _TRISA9 _NOT_ high impedance input at reset??? 2018/01/07 13:56:43 (permalink)
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AARRRgh! Thanks.
 
That's just too simple (and much easier than touching HW with all my thumbs)! I'll try it and let you know what happens!
 
 
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SirCut
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Re: PIC24F32KA304: _TRISA9 _NOT_ high impedance input at reset??? 2018/01/07 15:01:35 (permalink)
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OK @qyb. It looks like you were correct:
 
At first executable instruction I read expected TRISA (0-4, 6-11) as 1 (input).
For others' benefit, we now believe the PIC24F32KA304 data sheet TABLE 4-12 to be erroneous and reset state for TRISA SHOULD READ "0FDF", not "00DF" (as @qyb suspected). Good job.
 
Now it appears that maybe for my circuit input pin A9 may be damaged (or I don't understand something). Got any ideas, @qyb?
  • I have a P-Ch mosfet gate connected to RA9 (Also set TRISA9 as input ... [thanks])
  • This node (both gate and pin) are connected to Vdd (~= 2.3V) through a 1M pullup resistor.
  • However, voltage at this node measures 2.1V instead of the expected 2.3V!
 
It appears that about 200 nA (0.2V/1Mohm) of current is being drawn by the input pin RA9 ... any ideas? (I removed, checked, and replaced FET)
 
Hope this is not too out of line with the original posting. Trying to save power/current in this design.
 
Thanks again.
 
 
 
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Gort2015
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Re: PIC24F32KA304: _TRISA9 _NOT_ high impedance input at reset??? 2018/01/07 17:27:17 (permalink)
3 (1)
Not a good idea to rely on power on reset states.
 
You should still set trisx or clear trisx as needed.
Things may change in datasheets/bugs and even your own code may change.
 
 

MPLab X playing up, bug in your code? Nevermind, Star Trek:Discovery will be with us soon.
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+ ST:Continues, "What Ships are Made for", Q's back.
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SirCut
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Re: PIC24F32KA304: _TRISA9 _NOT_ high impedance input at reset??? 2018/01/07 17:54:35 (permalink)
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Thanks @Gort2015,
 
However, this is an energy harvesting application and I cannot control the state (code) when Vdd is lower than the operational state and even approaching zero. As energy is harvested the power supply will charge and I need to know the physics of the device even before code can run to set TRIS. Does this make sense? Or am I missing something?
 
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qɥb
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Re: PIC24F32KA304: _TRISA9 _NOT_ high impedance input at reset??? 2018/01/07 18:01:53 (permalink)
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Do you have the BOR enabled in the config word?
Yes, it takes a tiny bit more power when it is enabled, but should ensure your PIC stays in reset when the supply voltage dips too low.

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SirCut
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Re: PIC24F32KA304: _TRISA9 _NOT_ high impedance input at reset??? 2018/01/07 18:05:36 (permalink)
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No. BOR is disabled. I "learned" about this when trying to run the device down to 1.8V (per the spec) and it kept BOR at the defaul of (like) 1.95 V. 
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SirCut
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Re: PIC24F32KA304: _TRISA9 _NOT_ high impedance input at reset??? 2018/01/07 18:09:58 (permalink)
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Yes, BTW. Thanks @qyb.
 
I built a "supervisor" circuit with hysteresis so that the device stays in reset (~MCLR = 0) when the voltage is too low. It is under these conditions (under-voltage) that I need the input NOT to suck current!
 
 
 
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SirCut
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Re: PIC24F32KA304: _TRISA9 _NOT_ high impedance input at reset??? 2018/01/07 18:16:16 (permalink)
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But is should be noted that the device seems sink current even when it is well supplied with voltage (Vdd > 1.8V ). This is why I wonder if I damaged the input circuit. I did not have a current limiting resistor on the gate of the MOSFET driven by RA9 (driven after setting TRISA9 = 0 in initialization code after reset).
 
Thanks folks.
 
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qɥb
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Re: PIC24F32KA304: _TRISA9 _NOT_ high impedance input at reset??? 2018/01/07 18:45:20 (permalink) ☄ Helpfulby SirCut 2018/01/08 20:57:01
4 (1)
Yes, you may well have damaged the pin.
The capacitance of the gate pin may have overloaded it.
Only way to be sure is to swap out the PIC.
 

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SirCut
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Re: PIC24F32KA304: _TRISA9 _NOT_ high impedance input at reset??? 2018/01/07 20:06:41 (permalink)
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Thanks again, @qyb. Great to have your help. I think that you are right.  It will take some work to replace the uC. Don't know if it was my test equipment probing or because I did not have a current limiting resistor in series with the gate (to disallow over-current on the uC output pin).
 
This might serve as a warning to others:
Put a current-limiting series resistor inline when driving a FET gate from a uC output pin to avoid over-driving the output pin. 
 
(I now know that this is rather conventional to do, but I am only learning of it from the "school of hard knocks".)
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dan1138
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Re: PIC24F32KA304: _TRISA9 _NOT_ high impedance input at reset??? 2018/01/07 20:24:27 (permalink) ☄ Helpfulby SirCut 2018/01/08 20:57:18
4 (1)
You may be correct that the RA9 input is damaged but take a look in to the possibility that your circuit design may be causing a latch-up to occur.
 
Tough unlikely even a small current on any input can provoke a latch-up when VDD is in a marginal state.
 
For very low power designs it is simpler to have all inputs and outputs of the controller have the default power on state of zero volts. For inputs that must be pulled-up before reset is released they should on be pulled-up to the controllers VDD and not a power source that can be higher than VDD.
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SirCut
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Re: PIC24F32KA304: _TRISA9 _NOT_ high impedance input at reset??? 2018/01/07 22:12:21 (permalink)
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Thanks @dan1138,
 
Yes, I have a pullup (1 Mohm) on the input tied to Vdd (Vdd of the uC), as you suggest. Interestingly, I have an identical setup (output pin driving a power switch FET) on a different input pin that behaves properly. And yes, this is an XLP (extreme low power) design (attempt, anyway). The FETS driven by the output pins simply connect or disconnect subcircuits to save power when those subcircuits are not in use. I have heard of latchup but never really understood it. I will have to read and grok it.
 
Per your last statemen: "For very low power designs it is simpler to have all inputs and outputs of the controller have the default power on state of zero volts ..." I am not sure how you can make the power-on state of all outputs zero BEFORE ~reset is released. At that time, I think output buffer design automatically sets them all to Hi-Z. Indeed, I do set most to zero once initialization code is running.
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dan1138
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Re: PIC24F32KA304: _TRISA9 _NOT_ high impedance input at reset??? 2018/01/08 11:57:11 (permalink) ☄ Helpfulby SirCut 2018/01/08 20:57:35
5 (1)
SirCut
Per your last statemen: "For very low power designs it is simpler to have all inputs and outputs of the controller have the default power on state of zero volts ..." I am not sure how you can make the power-on state of all outputs zero BEFORE ~reset is released. At that time, I think output buffer design automatically sets them all to Hi-Z. Indeed, I do set most to zero once initialization code is running.

For my designs I use weak pull-down resistors and MOSFET transistor buffers for signals that connect to other voltage domains that must be powered when the controller is off.
 
There are buffer chips that can also be used to isolate signals between power domains but they tend draw more standby current than MOSFETs. They are useful when the signals need to switch faster than 10us.
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SirCut
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Re: PIC24F32KA304: _TRISA9 _NOT_ high impedance input at reset??? 2018/01/08 12:30:28 (permalink)
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Thank you, again Dan1138. Good general low-power design info.  My FETS used here are simple power switches (not signals). I am using high-side switches with P-channel enhancement MOSFET's with weak pullups to Vdd (vs grd) so that the reset Hi-Z input is pulled up to Vdd. Low-side N-channel switches might be better (and cheaper) but would keep my "sleeping" subcircuits at Vdd potential (vs grd). I'll have to think about/understand the trades.
 
Is there a convention or argument for using N vs P-channel FETS to switch off power supplied to subcircuits?
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dan1138
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Re: PIC24F32KA304: _TRISA9 _NOT_ high impedance input at reset??? 2018/01/08 13:09:48 (permalink) ☄ Helpfulby SirCut 2018/01/08 20:57:41
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When it comes to low power circuit design there are too many trade offs to consider for "general" guidelines or "rules-of-thumb" to be useful. When you have specific goals and performance in mind then more appropriate choices can be made.
 
As to a specific choice between a P-channel and N-channel FETs for power switching, it usually does not matter until the current that needs to be switch is in the several amperes range. In low voltage / low current applications having the lowest maximum RDS on resistance and maximum gate threshold voltage can be more critical. The next consideration is cost and availability of the parts.
 
Dual N-channel power FETs tend to be very low cost and readily available because every Lithium-Ion rechargeable battery pack on the planet has at least one in it.
 
On which power net to switch. Traditional thinking causes most designers to select power switching of the VDD power net. But the same voltage domain isolation issues exist when switching the VSS power net.
post edited by dan1138 - 2018/01/15 18:59:00
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SirCut
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Re: PIC24F32KA304: _TRISA9 _NOT_ high impedance input at reset??? 2018/01/08 20:58:59 (permalink)
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Much thanks, all. Excellent professional answers!
Smile: Smile
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