Thank you all for your suggestions.
I tried to implement the FIFO concept in the code but it does not work still.
I still get garbage value in the buffer that I am storing into even though the data on the MOSI line in the logic analyzer shows correct value.
But the value on the MISO line is different in the sense it does not shows what I am sending but instead is shows what I have received on the MOSI line and that too every alternate character.
For example from Master SPI I am sending ascii characters 0-9 followed by A-Z and then a-z I see this correctly on the MOSI line but on MISO line every alternate character is replaced by some fixed value sometimes 0x8A sometimes 0xE6 and others.
For example I get on MISO line : '138','s','138','u','138,'w','138,'y','138'.....
So if you see the characters in between the sequence are replaced by some constant character.
I am also providing ample delay on the Master SPI before pulling the CS line high so that slave does not miss any character.
Additionally I also tried providing a GPIO line between master and slave that is output on slave side and input on master side. So once the character is received I pull the line high so as to inform master not to send the next data buffer and only once the data is transfered to USART I pull the line low again.
This even did not work.
Below is what I tried to implement the FIFO concept:
if(inptr == outptr)
USART_puts("Buffer is empty\r\n");
spi[inptr++] = SPI_Read();
if((inptr+1) == outptr)
USART_puts("Buffer is full\r\n");
SSP1BUF = 0x55;
if(inptr == MY_BUFFER_SIZE)
inptr = 0;
if((inptr+1) == MY_BUFFER_SIZE)
inptr = 0;
if(outptr == MY_BUFFER_SIZE)
outptr = 0;
Even tried the concept that "Gort2015" suggested but even that did not work out.
Also you can run this fast or slow.
Have the slave send a busy state, read until ready.
What is missing is that you don't have any protocol, send commands to the slave.
What I don't get in this is when you say to send 4 bytes over from spi_slave before reading the 4 bytes.
When receiving the SPI data we can run the loop for SPI_read 4 times as it is going to get always new value uploaded in SSP1BUF .
But when we are writting 4 bytes to SSP1BUF in one go, the SSP1BUF is just going to get overwritten since slave cannot initiate the transmission and when master initiates the transmission it gets the byte and loads some value on the same SSP1BUF which we have to read to get it empty.
How would it work?
Lastly, the FIFO concept is only useful if I have to get a byte and forward the byte immediately to the USART to display.
But the application that I am trying to work is such that master SPI is going to send 240 bytes of data in one go which is supposed to be read by slave spi and send this over the USART to radio. In total there will 130 chunks of 240 bytes that SPI master is going to send and at the same time each chunk has to be sent to USART before another chunk is received by SPI slave.
Not sure how FIFO concept will solve this issue.