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JorgeF
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Re: what would you do with a dual core dspic? 2018/06/30 13:02:29 (permalink)
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Best regards
Jorge
 
I'm here http://picforum.ric323.com too!
And it works better....
JimDrew
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Re: what would you do with a dual core dspic? 2018/06/30 13:21:13 (permalink)
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Just a heads up for CH programmers.  ALL of the .inc files are missing ALL of the IPCx bit definitions!  I was trying to set an interrupt priority for CCP1 and kept getting an assembler error "undefined".  I went and checked the includes and all of the CH parts are missing the defines for IPC0, 1, 2, etc.  On all other PICs, these defines are located between the IECx and INTCONx bit definitions.  I am manually making the changes.  Sent a report to my friends at Microchip.
 
edit: also note that in Table 4-23 (Slave Interrupt Priority Registers) that the IPC21 entries for Bit2/Bit1/Bit0 are wrong.  Shown is PTG12P2/PTG12P1/PTG12P0.  They should be: PTG2IP2/PTG2IP1/PTG2IP0.
 
post edited by JimDrew - 2018/06/30 13:49:49
Gort2015
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Re: what would you do with a dual core dspic? 2018/06/30 13:49:13 (permalink)
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The include files are not available yet? .h and .inc
 
The div 6 cycle instruction is div2
Same instruction set used in M and S.

MPLab X playing up, bug in your code? Nevermind, Star Trek:Discovery will be with us soon.
https://www.youtube.com/watch?v=Iu1qa8N2ID0
+ ST:Continues, "What Ships are Made for", Q's back.
NorvisLM
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Re: what would you do with a dual core dspic? 2018/06/30 13:51:24 (permalink)
3 (1)
Gort2015
The include files are not available yet? .h and .inc

 
Available, but very premature. Missing a lot of definitions.
 
To name a few.....
Timer1 Extended Clock Select bits missing
Timer1 Input Clock Prescale Select bits missing
PWM Clock Divider Selection bits missing
PWM Master Clock Selection bits missing
Comparator Input Source Select bits missing
 
Slave Low-Power Operating Mode Status bits have typo
Smart Card Protocol Selection bit misspelled
 
There are more.
 
I'd take this version of the support files with a grain of salt.. for now.
post edited by NorvisLM - 2018/06/30 14:04:51
JimDrew
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Re: what would you do with a dual core dspic? 2018/06/30 13:54:16 (permalink)
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The includes files (.inc and the .gld) are there, but the .inc files are missing all of the bit definitions for the interrupt priority control registers (IPCx).  That is, so far.  I have not looked at what else might be missing.  I had to stop my coding to create the master and slave IPCx definitions.
 
The datasheet shows that the slave core uses only 6 cycles no matter what type of division instruction is used.  The datasheet author just neglected to add the foot note ID (2) after the 18/6. ie 18/6(2).
post edited by JimDrew - 2018/06/30 14:22:34
JimDrew
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Re: what would you do with a dual core dspic? 2018/06/30 14:13:20 (permalink)
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You might want to look in the includes.  A bunch of the clock select bit and other definitions were renamed.  For example, "CLKSEL0" was used in previous PICs.  For CCP1 that is now called "CLKSEL0_CCP1CON1L" (even though the datasheet states the bit should be called "CLKSEL0").
 
 
 
 
post edited by JimDrew - 2018/06/30 14:20:51
NorvisLM
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Re: what would you do with a dual core dspic? 2018/06/30 14:22:07 (permalink)
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@JimDrew
 
Yes, I am aware that names are appended to avoid collisions with other peripherals using same name, but I'm referring to definitions that just aren't there at all. Most often occurs with multi-bit field definitions.
 
I may want to sit this one out for a couple of months until the dust settles. The lack of PKOB support for the curiosity board has me pretty bummed although I added a header and am soldiering on with the PICKIT 3. I don't understand it as there is a MPLAB X screenshot that clearly shows someone at MC has this ability.
 
JimDrew
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Re: what would you do with a dual core dspic? 2018/06/30 14:24:55 (permalink)
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Yeah, it's a mess so far.  I would like to start flashing parts with REAL ICE but there doesn't seem to be a way to actually combine the slave core into the master core and do the flash.  I am waiting for Microchip to get back to me on that and numerous other issues discovered so far.
 
NorvisLM
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Re: what would you do with a dual core dspic? 2018/06/30 14:35:37 (permalink)
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@JimDrew
 
Within MPLAB X, under the PROJECTS Tab for the MASTER, there is a way to specify the associated SLAVE project.
 
I've made the linkage within the IDE but that's about as far as I've gotten to date.
 
Would love to know what MC says about this.
 
DarioG
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Re: what would you do with a dual core dspic? 2018/06/30 15:03:47 (permalink)
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thanks for this Norvis and Jim, I was exactly wondering "how goes the combine process"
post edited by DarioG - 2018/06/30 15:51:41

GENOVA :D :D ! GODO
JimDrew
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Re: what would you do with a dual core dspic? 2018/06/30 15:41:22 (permalink)
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edit: ok, I figured out how the assembly process works for the dual cores.  You go into the Project Properties (right click on the project name and select Properties or go to the pull-down menu under File and select Project Properties).  This is where you setup your assembler/compiler options.  You will notice if you have selected a project using core 0 that "slaves" is a new entry that is available.  Go to that entry and you can select the slave project.  Once you are done, anytime you assemble (and I suppose compile), the slave core will be assembled (or compiled) first, followed by the master core, and then the linker magically builds the single output file for debugging or programming.  I don't have the master core so it assembles yet (slave assembles fine) because of the various missing bit definitions.  Once it does and I can generate something that passes, I am going to see how it looks in the program memory window.  I *think* the slave code just gets put right after the end of the master core's program memory.
 
 
Oh man, just about every register has some bit definition missing!
 
The simulator shows 4 cycles for a BRA while using the slave core (it should be 2), and NONE of the interrupts so far (T1, CCP1, INT1, etc.) jump to the code that the IVT points to.  The int flag is set, but it does not go to the ISR.  I was hoping to determine how much latency there is with the slave core's interrupting handling.
 
One thing that really bothers me is that there is no "Use software breakpoints" option for REAL ICE when the CH parts are selected.  That means it is probably going to skid during debugging... ugh!
 
post edited by JimDrew - 2018/06/30 21:07:05
NorvisLM
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Re: what would you do with a dual core dspic? 2018/06/30 21:09:48 (permalink)
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Thanks Jim, I had specified a SLAVE in the Project Tree but the IDE wasn't doing anything with it. Following your lead, I checked the BUILD and DEBUG Checkbox under SLAVES in the Project Properties.
 
Have successfully compiled a combined MASTER/SLAVE project. The MASTER program runs fine and the IDE places the SLAVE code in MASTER Program Space immediately following the end of the MASTER code at label _Slave.
 
The SLAVE is given ownership of an LED connected to PORT RE1 via the configuration bits in the MASTER.
 
config __FCFGPRE0, CPRE0_MSTR & CPRE1_SLV1 & ……...
 
I'm using the library function __program_slave(core#, verify, &slave_image) to copy the program from MASTER FLASH memory to SLAVE PRAM memory.
 
         mov  #1, w0                            ; Core #1
         mov  #0, w1                            ; 0 = Program, 1 = Verify
         mov  #psvpag(_Slave), w2       ;  Slave Image Offset to w2
         mov #psvoffset(_Slave), w3     ; Slave image Page to w3
         call __program_slave
 
Finally a call to start up the slave.
 
         call __start_slave
 
 SUCCESS!!! I now have a MASTER Core running with Timer1 Interrupt blinking a LED on RE0 and the SLAVE core with essentially the same code blinking a LED on RE1.
 
Now on to some Intra-Core communication via the Master Slave Interface (MSI)
 
 
post edited by NorvisLM - 2018/07/01 19:27:34
JimDrew
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Re: what would you do with a dual core dspic? 2018/07/01 23:24:07 (permalink)
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Today I was able to get two projects assembled successfully.  I was able to set the physical address of where the slave code is stored in the master's program memory space using the ADDRESS option in the Project Properties.  I am guessing that if you don't set it then the linker sets it to be at the end of the master code.
 
I have to say I am a little disappointed.  The slave code occupies part of the master program's memory.  There is no dedicated memory for it, so it steals however much master program memory is needed to hold the slave program.  If your slave program was 24K it's going to steal that much of the master's program memory - meaning you don't have anything close to what you had originally.  For some reason I was thinking that the slave program was being stored in some additional program memory at the end of the master program's memory space.
 
So, as it stands right now, i can't use the 128 parts because they are too small.  I need at least the 256 parts.  I have been using 512 parts mainly because memory (both RAM and program space) was already pretty tight.  I have a lot of table data - like multiple 16K ROM pages of code that gets used for a CPU emulation.
 
I guess I will have to wait on using these parts for the purpose I was excited about until the 256 or 512 parts come out.
 
By the way, are you really using PSVPAG and PSVOFFSET?
 
I get this error when trying to assemble your example code above to copy the code from the master to the slave:
 
core0.s:578: Error: Too many operands ('mov #psvpag(_Slave),w2').
 
 
post edited by JimDrew - 2018/07/02 00:20:12
DarioG
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Re: what would you do with a dual core dspic? 2018/07/02 02:08:32 (permalink)
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Just noticed a little error in the datasheet: when showing PLL settings for oscillator, it says
200 MHz or 50 MIPS

which made me shiver for a while - do instructions take 2 or 4 cycles on these CPU? :)

No, it seems they still take 2 cycles, so all ok.

I also tried creating CONFIG bits from MPLAB, and it works for Master, and does nothing (empty window) for slave... without an alert :)

GENOVA :D :D ! GODO
Antipodean
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Re: what would you do with a dual core dspic? 2018/07/02 02:42:25 (permalink)
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JimDrew
So, as it stands right now, i can't use the 128 parts because they are too small.  I need at least the 256 parts.  I have been using 512 parts mainly because memory (both RAM and program space) was already pretty tight.  I have a lot of table data - like multiple 16K ROM pages of code that gets used for a CPU emulation.

 
But you could fit an external EEPROM (I2C or SPI) and have just a bootloader in the Master PROM that loads into the slave, then loads the slave code from external EEPROM. Guess this depends on your security requirements, but it wouldn't be impossible to have a decrypter as part of the bootloader and store the code encrypted in the EEPROM.
 
 

Do not use my alias in your message body when replying, your message will disappear ...

Alan
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Re: what would you do with a dual core dspic? 2018/07/02 04:44:01 (permalink)
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DarioG
Who uses debuggers, except in extreme issues? Smile
Go with 2 serial channels from the 2 cores...




I do, all the time. I need to hit breakpoints, not some blah blah (altough blah blah is nice to provide some form of trace..)
Haven't ordered board/chips yet :(
 
So, how can one debug the two cores simultaneously? Is it possible within MPLABX somehow?
DarioG
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Re: what would you do with a dual core dspic? 2018/07/02 04:48:31 (permalink)
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Of course I agree, but debuggers tend to be invasive or malfunctioning or both...
 
For "breakpoints", I toggle leds so I know code went through there; breakpoints on value - insert an if() and toggle led. If I need to check variables, I try to use RS232 or whatever "communication pipe" is available.
 
Call-stacks are something more though, when needed.

GENOVA :D :D ! GODO
NorvisLM
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Re: what would you do with a dual core dspic? 2018/07/02 07:57:32 (permalink)
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JimDrew
By the way, are you really using PSVPAG and PSVOFFSET?
 
I get this error when trying to assemble your example code above to copy the code from the master to the slave:
 
core0.s:578: Error: Too many operands ('mov #psvpag(_Slave),w2').


 
Yes, below is exactly as written in my successful code. (XC-16 1.35) 
Also, Page in w3, Offset in w2
 

 mov  #1, w0        ; Core 1
 mov  #0, w1        ; 0 = Program, 1 = Verify
 mov  #psvpage(_Slave), w3
 mov  #psvoffset(_Slave), w2
 
 call __program_slave
NorvisLM
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Re: what would you do with a dual core dspic? 2018/07/02 07:59:14 (permalink)
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DarioG
I also tried creating CONFIG bits from MPLAB, and it works for Master, and does nothing (empty window) for slave... without an alert :)



SLAVE config bits are specified in MASTER
NorvisLM
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Re: what would you do with a dual core dspic? 2018/07/02 08:06:03 (permalink)
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Jack_M
So, how can one debug the two cores simultaneously? Is it possible within MPLABX somehow?



Yes, but you will need two simultaneous ICD tools; one for MASTER and one for SLAVE.
 
ICD 3, PICKIT 3 are currently supported. ICD 4, PICKIT 4 are not but hopefully soon
 
 
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