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Jim Nickerson
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Re: what would you do with a dual core dspic? 2018/06/28 07:00:53 (permalink)
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still blinking post
DarioG
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Re: what would you do with a dual core dspic? 2018/06/28 07:02:39 (permalink)
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azz, it was my a p p l e thing the culprit!!

GENOVA :D :D ! GODO
DarioG
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Re: what would you do with a dual core dspic? 2018/06/28 07:03:23 (permalink)
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https://en.wikipedia.org/wiki/A p p l e_Worm
 
remove spaces...

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du00000001
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Re: what would you do with a dual core dspic? 2018/06/28 07:32:24 (permalink)
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                                                                                                                NorvisLM
 ... how does MPLAB X accomplish locating the Slave image within the Master Flash during ICSP?

 
I didn't dig into this, but I'd expect it to be similar to what's happening when you have some initialized variables in the global namespace (outside any function): during linking or HEX-File generation, the code is copied so some (most likely parameterizable) Flash area - from where the startup code copies this block to the PRAM.

PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)
marcov
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Re: what would you do with a dual core dspic? 2018/06/28 07:50:45 (permalink)
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Yes, probably certain sections specified in the linker script on some fixed address (so you can in theory increase master space if your slave program is small by adjusting that address).
 
At least that is how I would implement it.
JimDrew
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Re: what would you do with a dual core dspic? 2018/06/28 12:48:18 (permalink)
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Yes, it seems that the slave's PRAM can only be transferred from the master's flash memory, and that is at a fixed address.  There is no ability to load the PRAM from a SFR or RAM on the master core.  That's too bad.  It would have been nice to be able to load the slave's PRAM from an external flash rom, SD card binary, etc.  I am hoping that in the near future Microchip will have just a small (4K) boot segment for the master core with the general segment being PRAM like the slave core, and you could load both PRAMs using a special SFRs where could set an address and instruction to be transferred.  Work on this was disclosed at the Masters in 2014, along with the core being 100 MIPs.  It's taken awhile, but they are getting there.
 
The datasheet seems to imply that both cores can read any pin, but only one core can "own" (set) a pin.  If you can read it, does that also mean an interrupt can be generated for either (or both) cores?  I do like that they made individual change notification interrupts for each port instead of having a single change interrupt that handled all ports.  This makes it much easier to parse out and prioritize the interrupts associated with each port.
 
I am happy to see that the upcoming dsPIC33CH512 parts have 512K/48K (FLASH/RAM) for the master core, and 48K/16K (PRAM/RAM) for the slave core.  I don't think Microchip will put those into production until the first round of erratas are taken core of though.
 
The biggest downside I see to these new parts is:
 
Maximum current sunk/sourced by any 4x I/O pin is 15 mA.
Maximum current sunk/sourced by any 8x I/O pin is 25 mA
Output High Voltage Minimum is 2.4V, w/IOH > -8 mA
 
This means external buffering may be required in some cases.
 
post edited by JimDrew - 2018/06/28 13:59:42
NorvisLM
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Re: what would you do with a dual core dspic? 2018/06/28 14:08:12 (permalink)
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JimDrew
Yes, it seems that the slave's PRAM can only be transferred from the master's flash memory, and that is at a fixed address.  There is no ability to load the PRAM from a SFR or RAM on the master core.  That's too bad.  It would have been nice to be able to load the slave's PRAM from an external flash rom, SD card binary, etc.  


LDSLV Wso, Wdo, lit2
 
I see no such limitation. The LDSLV instruction use of Ws appears to offer tremendous flexibility in the source data; be it Master Flash, RAM, external SD, UART, SPI, Core Rope Memory, etc.
 
For Master to Slave image loading, the DSRPAG and
DSWPAG SFR registers are used in conjunction with
the Ws and Wd Working registers to create the source
and destination addresses for
LDSLV and VFSLV
instruction operations.

JimDrew
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Re: what would you do with a dual core dspic? 2018/06/28 14:28:10 (permalink)
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I was told that source/destination was restricted to the flash memory/pram memory.   The DSRPAG/DSWPAG SFR's are base addresses (banks) and the Ws/Wd are offsets added to the base addresses to make up the actual address.
 
The LDSLV instruction is executed by the Master user
application to transfer a single 24-bit instruction from
the Master Flash address, defined by Ws<14:0>
(DSRPAG), to the Slave PRAM address, defined by
Wd<14:0> (DSWPAG).

 
The Slave image instruction found at a given even
address should be loaded first. This will be the lower
instruction word of a 48-bit double instruction word. The
upper instruction word should then be loaded from the
following odd address. After the pair of LDSLV instructions
is executed by the Master user application, both
24-bit Slave image instructions and the generated 7-bit
ECC value are actually loaded into the PRAM destination
address locations.

 
This would seem to show that program memory to pram memory is the only possibility.  See Section 4.3 of the datasheet for more details.  This is what I was pointed to.
post edited by JimDrew - 2018/06/28 15:01:03
NorvisLM
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Re: what would you do with a dual core dspic? 2018/06/28 14:54:47 (permalink)
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@JimDrew
 
I see. Well since the SLAVE is capable of RTSP of its PRAM, a small bootloader loaded into the SLAVE allows an opportunity to load from SD and minimize the MASTER Flash footprint. 
NorvisLM
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Re: what would you do with a dual core dspic? 2018/06/28 15:01:27 (permalink)
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WOW!
 
microchipDIRECT just sent me a notification that my DM330028 Curiosity Board has shipped!
 
 
 
JimDrew
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Re: what would you do with a dual core dspic? 2018/06/28 15:02:36 (permalink)
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I agree!  Which is why I think just having a small master boot segment and all PRAM would be the way to go for the future.  The problem today is that the PRAM is pretty small until the 256 and 512 parts are released.
 
 
post edited by JimDrew - 2018/06/28 15:59:04
marcov
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Re: what would you do with a dual core dspic? 2018/06/29 01:46:59 (permalink)
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Indeed. Hmm, if there is more planned, will there be a 100 pin part too ? 80pin max seems a bit low for such a heavyweight
T Yorky
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Re: what would you do with a dual core dspic? 2018/06/29 05:54:04 (permalink)
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For info..
'Each read will fetch a 24-bit word from Flash and then effect a write of that word into the target Slave PRAM. A conventional dsPIC/PIC24 CPU architecture has no means to move data values larger than 16-bits from Flash, so the data is not moved through the Master CPU but captured...'
 
T Yorky.
NorthGuy
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Re: what would you do with a dual core dspic? 2018/06/29 06:44:46 (permalink)
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JimDrew
I agree!  Which is why I think just having a small master boot segment and all PRAM would be the way to go for the future.  The problem today is that the PRAM is pretty small until the 256 and 512 parts are released.



I think the idea is that you can program a small highly efficient program for the second core in assembler, and all the other stuff is running on the main CPU without interfering the fast second core processes.
NorvisLM
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Re: what would you do with a dual core dspic? 2018/06/29 06:54:55 (permalink)
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I received the dsPIC33CH Curiosity Board this morning and plugged a micro-USB cable into the PKOB connector. It powered up and appears to come with a burnt in application that varies the RGB LED color as a function of the POT position.
 
There is no documentation or source code provided with the kit. Additionally, there is no code posted online as of yet. Oh well, I'm not one to use MC code anyway and I moved on to a project I have been preparing over the past several days in anticipation of the board's arrival.
 
The PKOB is recognized by MPLAB X 4.20 but is not GREEN Lighted. (Arrrgh!) The PICKIT 3 and ICD 3 are GREEN Lighted but the PICKIT 4 and ICD 4 are not. My only other option is to install a 5 pin header on the board and proceed using a PICKIT 3. I have just one PICKIT 3 so I won't be able to simultaneously debug both cores until MC adds support for the dsPIC33CH PKOB and or PICKIT 4 in MPLAB X 4.21+.
 
Not sure why they didn't populate the 5 pin SLAVE Debug header as debugging the SLAVE does not appear possible without it; regardless of PKOB support or not.
 
DarioG
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Re: what would you do with a dual core dspic? 2018/06/29 06:58:52 (permalink)
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Who uses debuggers, except in extreme issues? Smile
Go with 2 serial channels from the 2 cores...

GENOVA :D :D ! GODO
JimDrew
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Re: what would you do with a dual core dspic? 2018/06/29 18:16:50 (permalink)
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I guess that depends on what you do.  I use REAL ICE for debugging just about every day.  But I am writing only in assembly, and cycle counting and optimizing everything.  I just got a 2nd REAL ICE so I can do the dual debug thing.
 
I agree that dual FTDI or CP2102 interfaces would be a super simple way for basic debugging.
 
The 512 parts are suppose to have 100 pin package options.  I don't know about 256, but I would think so.  I was surprised that the 48 pin QTFP was a 0.50mm pitch part.  That makes it smaller than a 44 pin QFN.
 
I was happy to see that the RTSP uses the DMA engine for automatic flashing (some PICs like the GM series have had this already).  You just point to block of RAM and where it needs to go in program memory, start it up, and it does everything for you.  You don't have the typical loop of writing to latches.  It's super fast this way.
 
Speaking of DMA engine, it looks like it should be possible to use the DMA on both cores to send/receive data through the mailboxes.  That would really fast way to share large volumes of RAM data if needed.  What I don't know with these new CPUs is how much stalling there is when the CPU is accessing any of the SFRs.  In the past, every time the CPU accesses a SFR the DMA is stalled for that cycle.  So, if you are polling a SFR you can kill your background DMA speed.
 
post edited by JimDrew - 2018/06/29 18:19:11
marcov
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Re: what would you do with a dual core dspic? 2018/06/30 06:14:14 (permalink)
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JimDrew: thanks for the info.
 
DMA speed is also one of my interest points (I have a W5500 attached for connectivity). A bummer is the low enhanced buffer queue depth, I used that to send simple commands to the w5500 asynchronously back-to-back bits. (DMA on MU814 has gaps between the byte/word elements ). I had hoped that would be more MK, 16 bytes usable maximally from every element size. (16 bytes, 8 words etc)
 
For the cycle counters: does running from pram reduce branch penalties ? That would make the slave more than just the 10% MIPS number faster.
 
 
JimDrew
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Re: what would you do with a dual core dspic? 2018/06/30 11:49:19 (permalink)
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Yes, the datasheet shows that all forms of BRA, CALL, GOTO, and RCALL are all worst case 2 cycles on the slave core, and 4 cycles on the master core.  RETFIE is 3 cycles on the slave core and 6 cycles on the master core.  All of these instructions are twice as fast on the slave core, so that definitely increases the speed quite a bit (besides being 10% faster already).  There are some other instructions that are also faster, like table reads.   TBLRDL/H take 3 cycles on the slave core and 5 cycles on the master core.  That makes pulling data from tables quite a bit faster, and that is something that is commonly used (at least by me).  This biggest difference though is the divide instruction.  All forms of DIV take only 6 cycles on the slave core.  However, the master core also has a few versions of DIV that also take just 6 cycles, with the rest being the normal 18 cycles.
 
I have been walking through code on the simulator today, checking out the differences.
 
NorvisLM
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Re: what would you do with a dual core dspic? 2018/06/30 12:43:25 (permalink)
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JimDrew
I have been walking through code on the simulator today, checking out the differences.



Good luck with that!
 
The simulator seems to stuff up the BFINS instruction by clearing all other bits outside of the field of interest. Execution with real hardware (Curiosity Board) seems to be as expected. I can only imagine what it might do to the new DIV instructions.
 
Also, there appears to be an inordinate number of typos and missing declarations in the .inc files for these parts.
post edited by NorvisLM - 2018/06/30 13:08:48
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