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du00000001
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Re: what would you do with a dual core dspic? 2018/06/17 15:08:19 (permalink)
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                                                                                                                                                           JPortici
I wonder, are you converting a SENT sensor to an analog one to interface with older equipment?

That's basically the purpose. As the input of the old equipment is 0-5 V, a 3.3 V device would require separate external amplifiers to adjust from3.3 to 5 V. The beauty of my PIC16 solution is in its single-chip approach: all components required are on-board - dual DACs, OpAmps and alike.
It's just when trying to implement "autobaud" features that 8 MIPS on an 8-Bitter isn't much - considering the typ. 5 µs low period of the SENT signal. And missing a packet is not really an option.
I started with a SENT test transmitter on a PIC16F15324 (which was at hand) and a first receiver using the 'EV starter kit. But 7-Bit DACs are not much when working vs. typ. 10-Bit ADCs. Which brought me to the '17xx. MAPS isn't that bad - although being  another nuisance :)
post edited by du00000001 - 2018/06/21 01:33:20

PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)
#61
NorvisLM
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Re: what would you do with a dual core dspic? 2018/06/20 08:52:11 (permalink)
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Gort2015
 
FLIM instruction?
MAX instruction?
BREAK instruction? stop code execution, looks like it stops it dead.
 
LDSLV - I can see that instruction as useful.
VFSLV - and that.
LAC.D and SAC.D - new.
new bitfield instructions.
 


 
FLIM is a saturation function
 
; Constrain 16-bit result to limits defined in W3:W4 (MAX:MIN)
; Write limit excess into W12
; Exit to Error if limits exceeded, else continue
MOV.L   #Result, W7 
FLIM.V  W3, [W7], W12 
BRA      NZ, Error
 
MAX and MIN instructions are similar but operate on ACC
#62
NorvisLM
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Re: what would you do with a dual core dspic? 2018/06/20 12:12:47 (permalink)
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du00000001
A bit speculative: most likely we'll need the '4s for this new type of device. If we're very lucky, the '3s will be updated 😎


To the contrary. MPLAB X v4.20 is showing support (GREEN) for the 3's and No Support (RED) for the 4's.
#63
Gort2015
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Re: what would you do with a dual core dspic? 2018/06/20 13:27:01 (permalink)
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@NorvisLM
Your example does not really explain it.
Can you point me to a datasheet that has those assembler instructions?

MPLab X playing up, bug in your code? Nevermind, Star Trek:Discovery will be with us soon.
https://www.youtube.com/watch?v=Iu1qa8N2ID0
+ ST:Continues, "What Ships are Made for", Q's back.
#64
NorvisLM
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Re: what would you do with a dual core dspic? 2018/06/20 13:53:46 (permalink)
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I'll try although this is still a bit speculative. My source is a Google translation of Microchip's Korean Patent Application.
 
FLIM.V  W3, [W7], W12
FLIM param1, param2, param3
 
FLIM will constrain the 16 bit signed value in param2 ([W7]), to the two 16 bit MIN and MAX limits specified in param1 (W4:W3).
The overage will be returned in param3 (W12).
 
FLIM.V will also set the ZERO Flag in the STATUS Register in the event of an overage.
 
I have yet to see a programmer's guide however, the simulator in MPLAB X v4.20 appears to support the CH parts for those wanting to get a head start with the new instructions. 
 
The Bit Field Insert (BFINS) instructions are a welcome addition as my current SetBits macro uses 14 instructions to accomplish the same result.
 
#65
MBedder
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Re: what would you do with a dual core dspic? 2018/06/20 13:55:54 (permalink)
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Not the datasheet yet but at least some info - http://www.freepatentsonl.e.com/y2016/0321202.html
post edited by MBedder - 2018/06/20 13:57:52
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Gort2015
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Re: what would you do with a dual core dspic? 2018/06/20 14:19:02 (permalink)
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I thought you had the datasheet for a second.
Still looking everyday.
 
Think I got it:
mov #'@',w2
mov #'+',w4
;
mov #'0',w0
mov #'9',w1
flim.v w0,w2,w3  ;7
flim.v w0,w4,w3  ;-5

 

MPLab X playing up, bug in your code? Nevermind, Star Trek:Discovery will be with us soon.
https://www.youtube.com/watch?v=Iu1qa8N2ID0
+ ST:Continues, "What Ships are Made for", Q's back.
#67
marcov
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Re: what would you do with a dual core dspic? 2018/06/20 23:55:49 (permalink)
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I looked at the spi bits a bit. I noticed while it says 50MHz spi without peripheral pin, it doesn't say anything about with peripheral pin. I also couldn't find anything about the enhanced buffer queue depth. (I assume 32-bytes like mk)
#68
du00000001
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Re: what would you do with a dual core dspic? 2018/06/21 00:56:28 (permalink)
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According to the datasheet, SPI FIFO is 4 bytes deep.
And SPI data rate via pins is up to 15 MHz via PPS pins resp. 40 MHz via dedicated pins.
 
RTF(riendly)M!

PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)
#69
Isaac_Sewell
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Re: what would you do with a dual core dspic? 2018/06/21 01:11:10 (permalink)
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T Yorky
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Re: what would you do with a dual core dspic? 2018/06/21 02:34:16 (permalink)
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@ NorvisLM
Just for your info, the PIC33/24 has always supported bit addressing. These are BSW.C/Z and BTST.C/Z. These allow indirect addressing of bit files and are also atomic (unlike a AND/OR mask sequence).
But in the few years working with these CPUs, I have never seen the compiler create these instructions. Maybe just supported in the licensed version.
The same applies to any new facilities/instructions. Very little benefit if the compiler does not use them (effectively).
Just not convinced there is a market for a device like this. Why not just go 32bit at higher freq. PIC33s are not exactly low power. 2 CPUs -> 60mA ? 
Now I've made that statement... the next Raspberry Pi will be based on one !!!!
(Pi-PIC .... patent pending)
post edited by T Yorky - 2018/06/21 02:36:10
#71
qɥb
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Re: what would you do with a dual core dspic? 2018/06/21 02:47:04 (permalink)
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Pican Pi? ;)
 

This forum is mis-configured so it only works correctly if you access it via https protocol.
The Microchip website links to it using http protocol. Will they ever catch on?
PicForum "it just works"
#72
marcov
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Re: what would you do with a dual core dspic? 2018/06/21 03:05:20 (permalink)
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du00000001
According to the datasheet, SPI FIFO is 4 bytes deep.
And SPI data rate via pins is up to 15 MHz via PPS pins resp. 40 MHz via dedicated pins.

 
I'm reading the CH128MP5 sheet, and page 605 says "up to 50MHz". The queue depth is on that same page so it is strange that I missed that. (much lower than expected though, I won't be able to stuff commands in it asynchronously that way)
 
I searched for the numbers you gave, and I see them on pg 750 in the same sheet. Maybe the 50Mhz is a copy paste from some generic sheet of this peripheral.  Anyway, I won't go that high anyway, but maybe it is worth reserving the dedicated one to do 20-25Mhz.
 
#73
JPortici
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Re: what would you do with a dual core dspic? 2018/06/21 03:34:48 (permalink)
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and weeeee haaaave a product page!!!!!
 
https://www.microchip.com...s/en/DSPIC33CH128MP508
#74
JPortici
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Re: what would you do with a dual core dspic? 2018/06/21 03:37:46 (permalink)
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Curiosity board available from 7th Jan '19, just like the chip. I really have to get in touch with my microchip guy, i want samples ASAP.
https://www.mouser.it/ProductDetail/Microchip-Technology/DM330028?qs=sGAEpiMZZMurRkjYD87c41V7S3LPQHfHMH2O1SAZ3wY=
 
What what about the RAdsPi?
#75
Isaac_Sewell
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Re: what would you do with a dual core dspic? 2018/06/21 04:00:58 (permalink)
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Ordered some from Farnell UK on Monday and they are apparently in the post for delivery tomorrow!
just tried to click on the product page and it's already gone. 
post edited by Isaac_Sewell - 2018/06/21 04:03:48
#76
du00000001
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Re: what would you do with a dual core dspic? 2018/06/21 04:30:35 (permalink)
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@ marcov
50 MHz on SPI might work out if the slave core is the SPI master - but only then as max. SPI frequency is usually core frequency / 2.
SPI communication between the cores circumvents the limitations imposed by the pin drivers and PPS delays, so this is plausible.

PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)
#77
JPortici
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Re: what would you do with a dual core dspic? 2018/06/21 04:35:31 (permalink)
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Isaac_Sewell
Ordered some from Farnell UK on Monday and they are apparently in the post for delivery tomorrow!
just tried to click on the product page and it's already gone. 




unfortunately, yes. Also now i can only see AVNET as a distributor on octopart :(
and neither the CH nor the CK are available at mouser anymore.
 
Nope, still there, just can't reach them through search. but i can still open the page from my browser history.
How much did they cost? i remember seeing 8euro something at farnell, 4 euro something at mouser
post edited by JPortici - 2018/06/21 04:38:25
#78
NorvisLM
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Re: what would you do with a dual core dspic? 2018/06/21 07:26:32 (permalink)
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@ T Yorky
 
BSW.C/Z and BTST.C/Z operate on single bits. Not very useful for setting a field of bits in the middle of a configuration register.
 
BFINS and BFEXT operate on a variable width field of bits and can save miles of code during configuration. Especially now that there are so many configuration registers.
 



#79
Isaac_Sewell
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Re: what would you do with a dual core dspic? 2018/06/21 08:00:10 (permalink)
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@JPortici: the Farnell order number is 2899559.  They don't appear on google, but if you search on the supplier they are there.  The uk price was £8.868, and I believe the European price is eur. 8.868.  In some ways, I feel ripped off.  In other ways, I have a new toy and anyway my company bought them.  I ordered 10.  Must try not to stroke them when I finally get hold of them!
The errata don't look too bad either.  Nothing wrong with the A/D which is a massive leap over the "GS" chips.
 
#80
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