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JPortici
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Re: what would you do with a dual core dspic? 2018/07/26 10:29:05 (permalink)
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I'd much rather have the old filenames if it also means old document layout/structure
JimDrew
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Re: what would you do with a dual core dspic? 2018/07/26 22:12:09 (permalink)
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I agree... renaming is easy to do - restructuring things in a PDF editor is a lot more time consuming!
 
JPortici
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Re: what would you do with a dual core dspic? 2018/07/28 03:13:33 (permalink)
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Meanwhile, the datasheet chapter for SPI is incomplete.
First, i couldn't find any mention of the SPIxBRG register. At least it's there on the reference manual.
Then: What is PBCLK? one could assume is FP (probably is, have to try). MCLK is probably the High Speed PWM Master Clock, but again a clear definition of the two has to be made.
 
Also, there are many peripherals that don't appear in the register maps (Master SFR Block and Slave SFR Block)
Edit: My mistake, they're there.
Regarding SPIxBRG, for example for SPI2
SPI2BRGL   ---xxxxxxxxxxxxx
SPI2BRGH   ----------------

 
post edited by JPortici - 2018/07/30 05:00:01
NorvisLM
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Re: what would you do with a dual core dspic? 2018/07/28 05:32:53 (permalink)
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Jack_M
Meanwhile, the datasheet chapter for SPI is incomplete.
First, i couldn't find any mention of the SPIxBRG register. At least it's there on the reference manual.
Then: What is PBCLK? one could assume is FP (probably is, have to try). MCLK is probably the High Speed PWM Master Clock, but again a clear definition of the two has to be made.
 
Also, there are many peripherals that don't appear in the register maps (Master SFR Block and Slave SFR Block)



PBCLK is defined in the Reference Manual as the Peripheral Clock, therefore I would have to agree with your assumption that it is Fp.
 
The datasheet and support files for these parts are a train wreck. Perhaps they threw the task to a summer intern.
JPortici
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Re: what would you do with a dual core dspic? 2018/07/28 05:39:15 (permalink)
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i suppose it's the same guy that mantains the PIC18 include files. the K42 series has wrong and duplicated interrupt flag bits, because they are leftovers from previous pics (altough it was """"okay""" until the K22, as they always were backwards compatible)
opened a ticket at every new compiler version since their introduction.
NorvisLM
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Re: what would you do with a dual core dspic? 2018/07/28 05:53:20 (permalink)
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Wouldn't this information all be linked to the part's hardware design database? With so many parts and so many definitions, I don't see how a corporation like Microchip could keep track of it all otherwise. A few simple Java utilities would provide automatic generation and verification for datasheets, support files etc. To the contrary, they appear to be manually generated.
DarioG
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Re: what would you do with a dual core dspic? 2018/07/28 06:07:52 (permalink)
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I actually fear it's java-automated wink

GENOVA :D :D ! GODO
Howard Long
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Re: what would you do with a dual core dspic? 2018/07/28 08:45:41 (permalink)
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DarioG
I actually fear it's java-automated wink


I’ve yet to see an example anywhere where automated documentation is what I’d call “good”.

The Harmony docs are good example of bad documentation generated by an automated copy and paste machine.
NorvisLM
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Re: what would you do with a dual core dspic? 2018/07/28 08:59:45 (permalink)
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I'm only suggesting that an automated tool could be used to generate File Register references in the Datasheets and Support Files to minimize the extent of initial errors. I have a simple 20 line utility that I have been using for years that parses the datasheet and creates initialization code (I don't use MCC). It took me 10 seconds to uncover no less than 50 errors in the dsPIC33CH .inc files.
 
 
post edited by NorvisLM - 2018/07/28 09:34:47
DarioG
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Re: what would you do with a dual core dspic? 2018/07/28 09:49:53 (permalink)
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Nice, Norvis!
Howard, I was pointing finger against java but... I also agree with your point. I've never read Harmony doc... only saw some examples on the forum...

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marcov
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Re: what would you do with a dual core dspic? 2018/07/31 00:36:21 (permalink)
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FYI yesterday I got a bit further with SPI+DMA (read+write using two channels) on the master core, and got something initially working. I had to enable enhanced buffer though.  The setup was a bit convoluted (jtag pins of explorer16 connected to a logic analyser), and I couldn't check real byte values. I ordered some empty pictail prints to build an real platform for testing.
 
And... contrary to dspic33e, no gaps between the elements.
post edited by marcov - 2018/07/31 09:31:02
JPortici
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Re: what would you do with a dual core dspic? 2018/07/31 06:31:47 (permalink)
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I am aslo playing with SPI these days. with variable lenght transferts to be more precise.
I am trying to implement a PIC programmer (since there is no USB and i wasn't able to find a USB bridge rated for 105/125°C, i want to add a PIC16LF1459 and program it from the 33CH so who is going to program the boards, hopefully not me, won't be going mad.)
 
the programming specification requires a 33bit word (32bit + another clock pulse) that i implemented as 16bit + 17bit transferts.
Then the commands are 6bit, data/answers are 16bit.
 
It took me a bit to wrap it up, so i hope it will be of help to somebody else, as this information is NOT in the datasheet or the reference manual.
 
In order to have > 16 bit transferts you have to be in 32bit mode. (MODE 32 = 1)
Then, set WLENGHT accordingly and start the transfert (write to SPIxBUFH before SPIxBUFL for > 16bit), the data has to be LEFT JUSTIFIED! and the size of the data changes with the lenght.
 
2-8 bit, the data has to be 8bit, left justified. (if you want to send 0x13 you have actually to write 0x4C)
9-16 bit, the data has to be 16bit, left justified.
17-32 bit, the data has to be 32bit, left justified.
 
I think it has to be left justified because the peripheral can shift the data from bit 8,16 and 32 only. Which make the code less clear that it could be, but surely the peripheral is much simpler this way.
 
And this is all the reference manual has to say on the matter, not even an example sad
3.3 Variable Word Length Operation
The SPI module allows variable word length when transmitting and receiving data over an SPI
bus. Word length can vary from 2 to 32 bits. Different word lengths can be configured by changing
the WLENGTH<4:0> bits (SPIxCON2L<4:0>). The number of clock pulses at the SCKx pin will
correspond to the word length that is selected.

marcov
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Re: what would you do with a dual core dspic? 2018/07/31 09:29:07 (permalink)
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This afternoon, I did a quick scan of the CANFD peripheral. Seems it is new. Couldn't find much, and the FRM has only two simple fragments.
 
What I did find is that the standalone CANFD device MCP2517FD  has pretty much the same registers, and even though interfaced from pic32MX over spi, the archive: MCP2517FD_canfdspi_API_v1.0.zip (just google it) can give some hints about how to setup the component.
 
I think I'll pass on that for now, and concentrate on my ethernet connectivity. (see last post, to interface Wiznet W5500)
JPortici
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Re: what would you do with a dual core dspic? 2018/07/31 10:36:50 (permalink)
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Yeah, they should be the same core, which is the kvaser CAN FD core so kvaser may have more info as well.
I will definetly test CAN, but after my vacation. I hope to be able to finish my PIC flasher so i can proceed to design my first prototype board with the dsPIC33C
JPortici
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Re: what would you do with a dual core dspic? 2018/08/01 04:52:49 (permalink)
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I just realized that the device doesn't actually have Dual Partition Flash.
I hoped i didn't have to add an external eeprom chip.
Howard Long
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Re: what would you do with a dual core dspic? 2018/08/02 09:15:18 (permalink)
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Jack_M
I just realized that the device doesn't actually have Dual Partition Flash.
I hoped i didn't have to add an external eeprom chip.


FWIW, the single core dsPIC33CK on the other hand does have dual partition flash. I've not tried it, I only just received the CK silicon today.
DarioG
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Re: what would you do with a dual core dspic? 2018/08/02 09:16:56 (permalink)
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obviously, the second partition became the second CPU Smile

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BLmicro
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Re: what would you do with a dual core dspic? 2018/08/02 11:18:57 (permalink)
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I like the dual core idea! I was going to pursue motor control with a Pic32 but setting it up to keep the essential real time events from being compromised can get messy as functionality grows. Nothing beats true parallel processing.
 
BUT! I have a question... The data sheet says 5 external interrupts but I only see INT0 on the pin diagrams. Are they configurable like Atmel's SAM devices or am I missing something?
 
-BL
JPortici
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Re: what would you do with a dual core dspic? 2018/08/02 11:37:30 (permalink)
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"configurable"
 
what do you mean?
 
INT0/S1INT0 is at a fixed position.
INT1/S1INT1 through 3 can be remapped to any RPxx or RPIxx (and S1RPxx or S1RPIxx) pin.
 
this mean that you have AT LEAST four external interrupt pins.
 
however i think that INT1-3 and S1INT1-3 can be remapped to different pins so you effectively have 4 EXTI for the master and 4 exti (3 of wich in different position if needed) for the slave.
 
However these are simple interrupts, they can also synchronize timers and other peripherals or initiate a DMA transfert but that's it.
 
However, if you need more pins you can generate interrupts on pin change on either or both directions with
- Peripheral Trigger Generator (master only)
- CLC (master and slave)
- Change notification interrupt (master and slave)
- Comparators (master and slave)
- possibly others
 
from the interrupt controller of the master and slave you see that your sources of interrupt that can behave like INTx are
- One per INTx: 4
- One per Port, Change Notification: Up to 5
- One per CLC per edge: 8 (4 positive 4 negative)
- One per Comparator: 1 for master, 3 for slave
- Others i can't think of right now
 
so at least 18 and 21 respectively...
 
now i suggest you try and at least make a sketch of your project, write pseudocode and look up what you need to know from each peripheral you're going to use... This is a very complex part and you may misread or misinterpret this or that paragraph and you don't want to find it out too late
BLmicro
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Re: what would you do with a dual core dspic? 2018/08/02 12:21:59 (permalink)
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By "configurable" I mean ability to remap as you described. Looks like it has what I need. Thank you!
 
-BL
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