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JorgeF
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Re: what would you do with a dual core dspic? 2018/07/20 17:01:13 (permalink)
4 (1)
Please stop flashing
 

Best regards
Jorge
 
I'm here http://picforum.ric323.com too!
And it works better....
JimDrew
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Re: what would you do with a dual core dspic? 2018/07/20 17:35:34 (permalink)
5 (1)
I was contacted today by Microchip asking what was needed for CH developers.  I made a request to get the rest of the CH specific FRM's released as well as the source code to the project that is flashed into the Curiosity board.  I am hoping that happens in the immediate future.
 
NorvisLM
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Re: what would you do with a dual core dspic? 2018/07/20 19:35:08 (permalink)
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JimDrew
I was contacted today by Microchip asking what was needed for CH developers.  I made a request to get the rest of the CH specific FRM's released as well as the source code to the project that is flashed into the Curiosity board.  I am hoping that happens in the immediate future.
 



ICD 4/PICKIT 4 support would be nice.
 
Also, some additional fidelity in the .inc files.
marcov
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Re: what would you do with a dual core dspic? 2018/07/21 03:14:41 (permalink)
3 (1)
Translated examples would be good. I wrestled with SPI under DMA, and couldn't get it working (I tried to send 100 bytes, but it would send only 4 even though enhbuf is off)
 
Below is my code, does sb see what is wrong?  I did some brief work with pic24f a decade ago, but in the end we chose dspic, and its SPI is different.
 
It's based on the PIM example and tries to do bidirectional send of 100 bytes over SPI using DMA every 50ms or so.
 

 
 
/* Standard libraries */
#include <stdio.h>
#include <stdlib.h>
#include <string.h>

/* 16-bit peripheral library for access to delay_ms() function. */
#include <libpic30.h>

/* Access to slave core image. */
#include "slave.h"

/* Access to the two demos that will run based on user selection. */
#include "app_master_pi_calc.h"
#include "app_slave_pi_calc.h"

/* Hardware access. */
#include "system.h"
#include "buttons.h"
#include "leds.h"

#include <xc.h>

#define nop5() { __builtin_nop(); __builtin_nop();__builtin_nop();__builtin_nop();__builtin_nop();}
#define nop25() { nop5() nop5() nop5() nop5() nop5() }
#define nop100() {nop25() nop25() nop25() nop25() }

#define  output_d3_Toggle()              {__builtin_btg((unsigned int *)&LATE,0);}
#define  output_d4_Toggle()              {__builtin_btg((unsigned int *)&LATE,1);}
#define  output_d5_Toggle()              {__builtin_btg((unsigned int *)&LATE,2);}
#define  output_d6_Toggle()              {__builtin_btg((unsigned int *)&LATE,3);}
#define  output_d7_Toggle()              {__builtin_btg((unsigned int *)&LATE,4);}
#define  output_d8_Toggle()              {__builtin_btg((unsigned int *)&LATE,5);}
#define  output_d9_Toggle()              {__builtin_btg((unsigned int *)&LATE,6);}
#define  output_d10_Toggle()              {__builtin_btg((unsigned int *)&LATE,7);}

#define output_3  LATEbits.LATE0
#define output_4  LATEbits.LATE1
#define output_5  LATEbits.LATE2
#define output_6  LATEbits.LATE3
#define output_7  LATEbits.LATE4
#define output_8  LATEbits.LATE5
#define output_9  LATEbits.LATE6
#define output_10  LATEbits.LATE7

#define FCY 90000000
#define BAUDRATE 115200
#define DEFBRGVAL ((FCY/BAUDRATE+2)/4)-1

#define SPI_CS LATEbits.LATE12
#define spilow 0
#define spihigh 1

#define inlinewrspi1(b) { SPI1BUFL = b; }
//{SPI1STATLbits.SPIROV = 0; SPI1BUFL = b & 0xff;  while (!SPI1STATLbits.SPIRBF); SPI1BUFL; }
#define inlinewrspi1rd(b,v2)  {SPI1STATLbits.SPIROV = 0; SPI1BUFL = b & 0xff;  while (!SPI1STATLbits.SPIRBF); v2=SPI1BUFL&0xff; }
#define inlinerdspi1(b)  {b=-1;  if (SPI1STATLbits.SPIRBF) {  SPI1STATLbits.SPIROV = 0; b= (SPI1BUFL & 0xff);  }   }
#define inlinewrpkt1(a,b,c) { SPI_CS = spilow;  inlinewrspi1(a); inlinewrspi1(b);inlinewrspi1(c); SPI_CS = spihigh; }
#define inlinerdpkt1(a,b,c) { SPI_CS = spilow;  inlinewrspi1(a); inlinewrspi1(b); inlinewrspi1rd(0,c); SPI_CS = spihigh; }



byte bufin[1024] __attribute__((eds, aligned(4)));
byte bufout[1024] __attribute__((eds, aligned(4)));

#define bufsiz 100

#define chen1too

void dmainit()
{
  DMACH0bits.CHEN=0; //Channel enable
  DMACH1bits.CHEN=0; //Channel enable

DMACONbits.DMAEN=1;
DMACONbits.PRSSEL=1;
DMAH=0x8000; //set lower and upper address limit
DMAL=0x800;
DMASRC0=(unsigned short int)& bufout; // load the source address
DMADST0=(unsigned short int)& SPI1BUFL; // load destination address

DMACNT0=bufsiz;
DMACH0=0;
DMASRC1=(unsigned short int)& SPI1BUFL; // load the source address
DMADST1=(unsigned short int)& bufin; // load destination address

DMACNT1=bufsiz;
DMACH1=0;

DMACH0bits.SAMODE=1; //Source address increment mode
DMACH0bits.DAMODE=0; //Destination address increment mode
DMACH1bits.SAMODE=0; //Source address increment mode
DMACH1bits.DAMODE=1; //Destination address increment mode

// spi1 rx int =2  spi1 tx int =3

DMACH0bits.TRMODE=2; //Transfer mode Continous
DMACH1bits.TRMODE=2; //Transfer mode Continous
 
 
 
// i've tried inverting this already.
DMAINT0bits.CHSEL=2;
DMAINT1bits.CHSEL=3;
DMACH0bits.SIZE=1;
DMACH1bits.SIZE=1;
//DMACH0bits.RELOAD=1;
//DMACH1bits.RELOAD=1;
DMACH0bits.CHEN=1; //Channel enable
#ifdef chen1too
 DMACH1bits.CHEN=1; //Channel enable
#endif
        
IFS0bits.DMA0IF=0;
IFS0bits.DMA1IF=0;
IEC0bits.DMA0IE=1;
IEC0bits.DMA1IE=1;

}

void spiinit()
{
    
_SPI1IF=0;
_SPI1IE         = 0;

    SPI1CON1=0;
    SPI1CON1H=0;
    SPI1CON2=0;
    SPI1CON2L=0;
    SPI1CON1Lbits.MCLKEN=0;
    SPI1CON1Lbits.DISSDI        = 0;    // no input pin
    SPI1CON1Lbits.DISSCK        = 0;    // 0 = Internal SPI clock is enabled
    SPI1CON1Lbits.DISSDO        = 0;    // 0 = SDOx pin is controlled by the module
    SPI1CON1Lbits.MODE32        = 0;    // 1 = Communication is word-wide (16 bits)
    SPI1CON1Lbits.MODE16        = 0;    // 1 = Communication is word-wide (16 bits)
    SPI1CON1Lbits.SMP        = 0;    // 0 = Input data sampled at middle of data output time
    SPI1CON1Lbits.CKE        = 0;    // 0 = Serial output data changes on transition from Idle clock state to active clock state (refer to bit 6)
                                    // The CKE bit is not used in the Framed SPI modes. Program this bit to ?0? for the Framed SPI modes
    SPI1CON1Lbits.CKP        = 0;    // 0 = Idle state for clock is a low level; active state is a high level
    SPI1CON1Lbits.MSTEN        = 1;    // 1 = Master mode
    SPI1CON1Lbits.SSEN        = 0;    // 0 = SSx pin not used by module. Pin controlled by port function

    SPI1BRGH =0;
    SPI1BRGL =4;     // 90 / (2*4+1)
             
    SPI1CON2bits.FRMEN         = 0;     // 1 = Framed Mode Enabled
//    SPI1CON2bits.FRMSYNC    = 0;     // 0 = Frame sync pulse output (master) (in 510)
    //SPI1CON2bits.SPIFSD        = 0;     // 0 = Frame sync pulse output (master) ( in 804 en E)
   // SPI1CON2bits.FRMPOL        = 0;     // 1 = Frame sync pulse is active-high
   // SPI1CON2bits.FRMDLY        = 0;     // 0 = Frame sync pulse precedes first bit clock
    SPI1CON1Lbits.ENHBUF      =0;
     SPI1CON1Lbits.SPISIDL    = 0;    // Continue module operation in Idle mode

    SPI1CON2Lbits.WLENGTH=0; // 7=8bits 0= use mode16/32 bits in SPI1CON
    IPC2bits.SPI1RXIP=3;
    IPC2bits.SPI1TXIP=2;
    SPI1IMSKLbits.SPITBEN  = 1;
    //SPIRBFEN = 1;
    //SPI1IMSKLbits.SPITBFEN   = 1;
}
int main ( void )
{ byte b =32;     
  word bb;
 

    /* Initialize the clock and board hardware. */
    SYSTEM_Initialize();
    ANSELA=0;
    ANSELB=0;
    ANSELC=0;
    ANSELD=0;
     
    /* Program and start the slave core image. */
    _program_slave(1,0,slave);
    _start_slave();

    for (bb=0;bb<sizeof(bufout);bb++)
    {
        bufout[bb]=bb;
    }
    bufout[0]=1;
    bufout[1]=3;
    bufout[2]=7;
    bufout[3]=15;
    bufout[4]=31;
    bufout[5]=63;
   // uartinit(DEFBRGVAL);
    /* Clear the LCD screen. */
    //printf("\f");
    
    LED_Enable(LED_D10);
    LED_Enable(LED_D3);
    LED_Enable(LED_D4);
    LED_Enable(LED_D5);
    LED_Enable(LED_D6);
    LED_Enable(LED_D7);
    LED_Enable(LED_D8);
    LED_Enable(LED_D9);
        


 //   uartenable();
   
 CCP1CON1L=0;
CCP1CON1Lbits.CLKSEL=2;
CCP1CON1Lbits.T32=1; // must be set before 32-bit regs are written.

// MOD=0
CCP1CON1H=0;
CCP1CON2L=0;
CCP1CON2H=0;

CCP1CON3H=0;

CCP1TMRL=0;
CCP1TMRH=0;
CCP1PRL=0x0000;
CCP1PRH=0x1000;

// sck1 =6 sdo1=5 op zowel e-mu als ch

RPOR13bits.RP58R=5;  // rp58/rc10/pin66 sdo1
RPOR13bits.RP59R=6;  // rp58/rc11/pin67 sCK1
RPINR20bits.SDI1R=65;
TRISCbits.TRISC10=0;
TRISCbits.TRISC11=0;
TRISEbits.TRISE12=0;

TRISDbits.TRISD1=1;
 
spiinit();
dmainit();
SPI1CON1Lbits.SPIEN    = 1;    // Enables SPI1 module
    
SPI1STATLbits.SPIROV = 0; // (3))

IEC0bits.CCT1IE=1;
CCP1CON1Lbits.CCPON=1;
    while(1)
    {
        output_d3_Toggle();
    //__delay_ms(50);
    
    DMACH0bits.CHEN=0; //Channel enable
    DMACH1bits.CHEN=0; //Channel enable

DMADST1=(unsigned short int)& bufin; // load destination address
DMASRC0=(unsigned short int)& bufout; // load the source address
DMACNT0=bufsiz;
DMACNT1=bufsiz;
DMACH0bits.CHEN=1; //Channel enable
#ifdef chen1too
  DMACH1bits.CHEN=1; //Channel enabl
#endif

    SPI1STATLbits.SPIROV =0;

    DMACH0bits.CHREQ=1; //Enable the transfter by software trigger
    while(!DMAINT0bits.HALFIF); //HALFIF=1 is set when
    //DMACNT0 reaches halfway
    output_d5_Toggle();
    
    nop5();
     
    while(!DMAINT0bits.DONEIF)
    {
        if (!DMAINT0bits.DONEIF)
        { output_6=1;}
        else
        { output_6=0;}
        
        if (!DMAINT0bits.HALFIF)
        { output_7=1;}
        else
        { output_7=0;}
        output_d8_Toggle();    
    }
   // __delay_ms(1);
    
    nop100();
    nop100();nop100();
    nop100();
    nop100();nop100();
    IFS0bits.DMA0IF=0;
    IFS0bits.DMA1IF=0;
    DMAINT0bits.DONEIF=0;
DMAINT0bits.HALFIF=0;
DMAINT1bits.DONEIF=0;
DMAINT1bits.HALFIF=0;
    _SPI1IF=0;  
    _SPI1TXIF=0;
    _SPI1RXIF=0; 
               
    }


}

void __attribute__ ((interrupt,no_auto_psv)) _CCT1Interrupt(void)
{
 output_d4_Toggle()                
    IFS0bits.CCT1IF=0;
}

void __attribute__((interrupt, no_auto_psv)) _DMA0Interrupt(void)
{
      IFS0bits.DMA0IF = 0;        // Clear the DMA0 Interrupt Flag;

}



void __attribute__((interrupt, no_auto_psv)) _DMA1Interrupt(void)
{
    IFS0bits.DMA1IF = 0;        // Clear the DMA0 Interrupt Flag
}

void __attribute__((interrupt, no_auto_psv)) _SPI1RXInterrupt(void)
{
    IFS0bits.SPI1RXIF=0;
 
}

void __attribute__((interrupt, no_auto_psv)) _SPI1TXInterrupt(void)
{
 
    IFS0bits.SPI1TXIF=0;
}

 
p.s. the errata might also do with some work. Only errata for one or two peripherals is fishy.
p.p.s. Anything about interrupt latency would also be nice. pic32mk had a paragraph about it in the datasheet.
post edited by marcov - 2018/07/21 03:18:17
DarioG
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Re: what would you do with a dual core dspic? 2018/07/21 03:57:16 (permalink)
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I've got a side question:
am I allowed to read a PORT from, say, slave, if MAster owns it? In other words, I suppose "ownership" is only for writing, but...

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qɥb
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Re: what would you do with a dual core dspic? 2018/07/21 04:11:30 (permalink)
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Wouldn't it be quicker to test it yourself, then you could tell us... ;)
 

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The Microchip website links to it using http protocol. Will they ever catch on?
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NorvisLM
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Re: what would you do with a dual core dspic? 2018/07/21 06:02:15 (permalink)
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Quicker yet to read the DS, Section 3.6  :)
 
Note: The output functionality of the ports is
defined by the Configuration registers,
FCFGPRA0 to FCFGPRE0. When these
Configuration bits are maintained as ‘1’, the
Master owns the pin (only the output function); when the bits are ‘7’, the ownership of
that specific pin belongs to the Slave.


The input function of the I/O is valid for both
Master and Slave. The Configuration
registers, FCFGPRA0 to FCFGPRE0, do
not have any control over the input function.

post edited by NorvisLM - 2018/07/21 06:19:54
DarioG
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Re: what would you do with a dual core dspic? 2018/07/21 06:04:57 (permalink)
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thanks you both grin
Yeah, I was going to test it: I just wanted the slave to "follow" a pin driven by the master and replicate onto another pin. Just to see...

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Antipodean
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Re: what would you do with a dual core dspic? 2018/07/21 09:36:54 (permalink)
4 (1)
FaulknerPD
Quicker yet to read the DS, Section 3.6  :)
 
Note: The output functionality of the ports is
defined by the Configuration registers,
FCFGPRA0 to FCFGPRE0. When these
Configuration bits are maintained as ‘1’, the
Master owns the pin (only the output function); when the bits are ‘7’, the ownership of
that specific pin belongs to the Slave.


The input function of the I/O is valid for both
Master and Slave. The Configuration
registers, FCFGPRA0 to FCFGPRE0, do
not have any control over the input function.





I guess that means a pin can be used as in interrupt to both cores, allowing a panic interrupt to stop them both.
 
 

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JimDrew
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Re: what would you do with a dual core dspic? 2018/07/21 23:08:28 (permalink)
4.5 (2)
I spent some time with the MSI (Master-to-Slave Interface) today.  Microchip's datasheet is extremely confusing, talking about block protocols and such.  Let me save you some headache...
 
There are 16 mail boxes.  These are SFR's that are a word wide.  You can program the data direction to be either master to slave or slave to master for each mail box individually.  The selection is done with a CONFIG register, meaning that there is no ability to change the mail box data direction at run time!  You are stuck with what you flash it with.
 
These mail boxes can be written to by the "transmitter", and read by either the transmitter or "receiver".   The receiver can not write to a mail box.  These ports are active immediately.  You don't have to do anything other than set the CONFIG register for the proper M2S or S2M designation.
 
Now, the confusing part (at least for me) is that you don't need an interrupt and you don't need assign a protocol block in order to have complete access to the mail boxes.  The ONLY thing that setting a protocol block type will do for you is generate an interrupt (on the receiver side) for the mail box that has been setup to generate the interrupt.  You can choose up to 8 of the 16 mail boxes to generate an interrupt.  The example in the MSI FRM shows writing to several mail boxes that don't have protocol blocks/interrupts assigned to them, and then writing to a mail box that does have a protocol block/interrupt assigned to it.  This is used as a handshaking method.  The interrupt that is generated by writing to the mail box with the protocol block assigned to it will guarantee that the contents of the other mail boxes will be there because they were written prior to the last one that caused the interrupt.  Whew!  In my case, the master is just reading the slave's mailbox directly without interrupts.  By reading the mail boxes directly I don't have any interrupt overhead.  There is no mention of issues using RMW (read-modify-write) instructions with the mail box registers, but I did not test this.
 
There is also a single 2-channel, word-wide FIFO register.  You can set this up to use interrupts (or not).  You write to a special register on the master core and it appears on a special register on the slave core (and vice-versa).  In my project I am using an interrupt for this (on the slave side) so that the master core can fetch RAM variables from the slave core.  I deal with single bytes of data, so I setup my variables as a table of bytes in the slave RAM.  On the master core I send a word to the FIFO register.  The lower byte contains the offset in RAM (up to 6 bits worth of address space) to read/write.  The 7th bit is a READ/WRITE flag.  The upper byte contains a byte to write (if it's a WRITE command) or nothing it's a read command.  A READ command causes the slave to send back the value requested using the same format.  It works pretty well.  Note that you can not use any RMW instructions on FIFO directly.  The FIFO is up to 32 words deep.  You just write/write/write/... to the same register sequentially and you do a read/read/read/... of the equv. register on the other side.  Pretty simple really.  This would be a really fast and transparent way to send large amounts of changing data from one side to another using DMA.
 
I still can't determine the actual latency of anything because REAL ICE doesn't have a correct stop watch function. I should probably setup a timer and toggle some pins on my scope to measure the actual latency.
 
I have asked about the Pickit 4 support.
 
 
post edited by JimDrew - 2018/07/21 23:28:30
JPortici
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Re: what would you do with a dual core dspic? 2018/07/22 01:44:07 (permalink)
3 (1)
spotted on the MPLABX 5.00 device support list
 
dsPIC33CH512MP508,dsPIC33CH256MP508 and others
DarioG
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Re: what would you do with a dual core dspic? 2018/07/22 02:12:20 (permalink)
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Interesting, thanks Jim Smile

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JimDrew
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Re: what would you do with a dual core dspic? 2018/07/23 10:20:55 (permalink)
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Looks like MPLAB5.00 might support Pickit 4.
 
Many of the CK series MCU's are now available for sale on MicrochipDirect as well as Digikey, Mouser, etc.
 
Looks like the CK series is missing the 2nd core, but uses the 2nd core's peripherals.  Like there are 3 I2C interfaces (where the CH has 2 for the master and 1 for the slave).  The CK series is pin compatible.  I am curious about what "LiveUpdate" is.  There is no mention of it anywhere in the datasheet except the first page of specs.
JPortici
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Re: what would you do with a dual core dspic? 2018/07/23 12:44:56 (permalink)
3 (1)
yes, i came to the same conclusion.. the set of peripherals is the same, CK and CH are the same part, single and dual core.
 
Live Update, i think it refers to the dual-panel flash, you can update the inactive partition without stalling the core
 
https://www.youtube.com/watch?v=Y7cOUCQ5yEM
JPortici
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Re: what would you do with a dual core dspic? 2018/07/23 12:48:22 (permalink)
3 (2)
UPDATED PROGRAMMER REFERENCE MANUAL
 
http://ww1.microchip.com/...eviceDoc/70000157g.pdf
post edited by JPortici - 2018/07/23 12:49:50
Howard Long
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Re: what would you do with a dual core dspic? 2018/07/25 09:11:08 (permalink)
3.5 (2)
A couple of pairs of projects for the dsPIC33CH Curiosity board
 
Stereo Blinky (of course) http://www.howardlong.com/files/d33chCuriositySG001.zip
Ultra simple Master to Slave mailbox example http://www.howardlong.com/files/d33chCuriositySG002MSI.zip
 
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Re: what would you do with a dual core dspic? 2018/07/25 13:55:48 (permalink)
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Howard Long
A couple of pairs of projects for the dsPIC33CH Curiosity board
 
Stereo Blinky (of course) http://www.howardlong.com/files/d33chCuriositySG001.zip

 
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Re: what would you do with a dual core dspic? 2018/07/25 14:08:47 (permalink)
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the only good answer to this planet's inhabitants is "why don't you just die?"
post edited by DarioG - 2018/07/26 10:15:17

GENOVA :D :D ! GODO
JPortici
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Re: what would you do with a dual core dspic? 2018/07/26 07:01:26 (permalink)
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Today i finally had some time to play with the curiosity board :)
 
Fisrt of all, I hate to remark how much i HATE the new documentation format. The high speed PWM reference manual. which by the way isn't locked, maybe i should change it to my liking. many pages wasted for one line of text, you could easily reduce it by at least 20 pages.
 
Second, i played a bit with the PWM, i can use it to mimic a CCP and generate single pulses at my liking. Actually, with more flexibility than with the CCP module (see dsPIC33EV, dsPIC33EP MU series)
 
I can use the PWM to generate SENT signals mr green: mr green i feared it wouldn't be really possible, because of how the HSPWM work in the aforementioned dsPICs. Or maybe it's possible with some effort, but i didn't have to because i had plenty of OCs, which are lacking here (all the SCCP modules will be used as input capture in this project)
 
Third, the DACs seem to be useful. Measurements on the direct outputs are promising (settles in around 1us, sine wave distortion is low, altough the INL/DNL isn't stellar) altough a bit noisy, but that's a combination of very high frequency noise generated by the dac, easily filtered out, and EMI and other crap picked up by the curiosity board. I have to make a proper board soon..
 
I attached a picture of the current test firmware, a simulated SENT sensor (bogus data in fast and slow channels) and a 1kHz at 100kSps sine wave using the dac.
Again, most of the noise come from the demo board and all the EMI crap around here
 

Attached Image(s)

Howard Long
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Re: what would you do with a dual core dspic? 2018/07/26 09:18:13 (permalink)
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For me the format of the new documents is too sparse, I agree that I preferred the old format where information was more densely packed.
 
On the plus side, at least they are starting to use file names that mean something. I don't even want to think about the amount of time I've wasted renaming their files into something meaningful, plus the amount of time randomly opening files with meaningless numeric file names. (TI desperately needs to address this too). While the numeric file names might have suited Microchip's internal content management systems, it's useless for customers.
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