I would never trust a I2C simulator (with all due respect to Proteus... )

Make real hardware, get TC74...

DarioG
Make real hardware, get TC74...

what u may not notice is that i use simulator and hardware too . this schematic of the bitmap file i upload before i have it in real and i download the code for both master and slave but i get the same result general call zero . address match interrupt zero start stop interrupts work fine . simulation and hardware results are matched here https://imgur.com/Jx3c65z

if i am not mistaken i guess i found something 

17.4.10 I2C MASTER MODE TRANSMISSION
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the Buffer Full flag bit, BF and allow the Baud Rate
Generator to begin counting and start the next
transmission. Each bit of address/data will be shifted
out onto the SDA pin after the falling edge of SCL is
asserted (see data hold time specification
parameter 106). SCL is held low for one Baud Rate
Generator rollover count (TBRG). Data should be valid
before SCL is released high (see data setup time
specification parameter 107). When the SCL pin is
released high, it is held that way for TBRG. The data on
the SDA pin must remain stable for that duration and
some hold time after the next falling edge of SCL. After
the eighth bit is shifted out (the falling edge of the eighth
clock), the BF flag is cleared and the master releases
SDA.

i get this  from datasheet look to the next screenshot in the link 
this first screen for the not ack signal https://imgur.com/T8R74GL
 
this screen for one of the data signal https://imgur.com/HcRLZ1a
 
check them both and check the quote above of the datasheet about the transmission and tell me ur notes  pls 

qhb
No labels on the graphs.
No description of what you expected to see, and what you think is relevant.
Now I think you're just being lazy.
I don't see anything in that text that goes against what you've already been told.
 

In the text they say that data bit should be ready while clock bit is 0 and before it turns to 1 then it should stay steady after the clock bit goes to 0 alittle time then the next data bit is going to be prepared same as the previous data bit one . the only data bit who goes according to that description is the ackwonledge bit the rest of data bits starts to be ready while clokc bit is equal to zero and the goes to zero in the same time the clock bit goes to 0 
i just didnt want to imply my opinion on u and wanted u to see it by ur self . i am not lazy at all thank u 

ubuntumanIn the text they say that data bit should be ready while clock bit is 0 and before it turns to 1 then it should stay steady after the clock bit goes to 0 alittle time then the next data bit is going to be prepared same as the previous data bit one . the only data bit who goes according to that description is the ackwonledge bit the rest of data bits starts to be ready while clokc bit is equal to zero and the goes to zero in the same time the clock bit goes to 0

Not clear what you want to express and then, how this helps to solve your problem now.  The data bits must be valid at the rising clock. Did you read my proposed i2c tutorial ?
https://support.saleae.co...ter-Integrated-Circuit
Besides it's not very likely that the master's i2c hardware could not correctly transfer a byte (once started).
 

Just fyi... in all the slaves I've done using the MSSP I've never had to "shift the address byte".
 
If your master is sending 0x30 as the slave address (R/W_ = 0), then load 0x30 into the slave SSPADD reg.
Remember bit 0 is the R/W_ bit, so keep it cleared.
 
Also, if you're using the General Call address make sure you're not falling into this trap http://www.microchip.com/forums/m595338.aspx
 

Just took a quick look at a dsPIC I'm using these days and... it seems that the address loaded into Slave's address register must be the "real" one, while Master will send it shifted along with the r/w bit...

DarioJust took a quick look at a dsPIC I'm using these days and... it seems that the address loaded into Slave's address register must be the "real" one, while Master will send it shifted along with the r/w bit...

That's what I do with two PIC24FJ256GB406 (master and slave) (and its working).
I think Jerry did not really say something different, but it could be misunderstood.

ubuntuman
 
He says to put 0x18 in master and 0x18 in slave not 0x30 in master and 0x18 in slave 

Yep, while we say put 0x30 in master and 0x18 in slave :)