Hot!Ring modulator DDS sine generation whine in output from DAC MCP4822

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2017/09/13 04:04:03 (permalink)
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Ring modulator DDS sine generation whine in output from DAC MCP4822

Hi all,
Firstly, I am new at this, so please be gentle. I wasn't sure which forum to post in, but the processor is a dsPIC33FJ128GP802, and MPLabX with the latest free version of XC16 (1.32) so here it is.
 
I am building a ring modulator for voice. I have the code working, using basic DDS to generate the sine wave as the modulating input. Sine frequency is set by jumpers/switches from a table of frequencies. The internal DAC was too noisy, so I changed to a MCP4822 SPI DAC, which has solved the noise issue. My problem now is that at low frequencies (25 Hz currently) I get a high pitched whine in the audio output. If I use the ADC for voice and modulate send that out the DAC nmodulated, it is clean. If I set the sine table at all zero's (2048 in this current code), I get silence. That tells me that the analog output is fine, and the SPI to the DAC is fine. Using the code published here, I send the generated sine directly to the DAC, and I get a high pitched whine over the top of the low frequency sine.
 
I don't know how to track it down from here. This is hobby stuff, not commercial. Any help is much appreciated.
 
 

#include <xc.h>
#include <stdio.h>

#pragma config FNOSC = FRCPLL //Internal RC Osc w/PLL (RC+PLL)
#pragma config POSCMD = HS //HS osc mode
#pragma config FWDTEN = OFF //

#define FOSC 73728000 // Hz
#define FCY (FOSC/2) // Hz
#define FVCO (2*FOSC) // Hz

// Sampling Control

#define Fs 48000 // Hz
#define SAMPPRD ((FCY/Fs)-1) // cycles per sample
#define NUMSAMP 256

// Misc defines

#define TP LATBbits.LATB5 //pin 14 for testing
#define cs LATBbits.LATB3 //Pin 7 for SPI1 chip select
#define JP1 PORTBbits.RB15 //Jumper 1
#define JP2 PORTBbits.RB14 //Jumper 2
#define JP3 PORTBbits.RB13 //Jumper 3
#define JP4 PORTBbits.RB12 //Jumper 4
#define JP5 PORTBbits.RB11 //Jumper 5
#define JP6 PORTBbits.RB10 //Jumper 6

#include <libpic30.h> //Must be declared after FCY is defined

// Functions
void Pin_Init(void);
void spi_init(void);
void timer2_init(void);
void timer3_init(void);
void modfreq_init(void);

// Peripheral ISRs

void __attribute__((interrupt, no_auto_psv)) _T2Interrupt(void);
void __attribute__((interrupt, no_auto_psv)) _T3Interrupt(void);

//Variables

int sine_i = 0; // index to track position in the sine wave array
volatile unsigned long phaseaccum = 0; //DDS phase accumulator
char rollover = 0; //Phase accumulator has rolled over
unsigned long tuningword; //Tuning word for DDS sine generation 50Hz?
int modvalsel = 1;
unsigned long modvalinc = 15238000; //Tuningword value per hertz audio modulation
//char domeled; //Dome light variable
int dummy; //Dummy SPI
int mod_audio; //Generated sine value for modulating ADC input audio
int dac_mod_audio; //Audio sample processed for external DAC
long int unprocessed_audio; //Temp holds unprocessed audio
long int div_audio; //Audio shifted to reduce back into DAC range after multiplication
long int processed_audio;
unsigned int data;
unsigned int dipsw; //Frequency setting variable

void Pin_Init(void)
{
    TRISB = 0b1111000000000001; //RB15, 14, 13, 12, 0 as inputs
    OC1CONbits.OCM = 0b000; // Disable Output Compare Module 1
    OC2CONbits.OCM = 0b000; // Disable Output Compare Module 2
    CNPU1 = 0b1111100000000000; //Setup weak pullups on pins 21-16
    CNPU2 = 0b0000000000000001; //Setup weak pullups on pins 21-16
    // Unlock so that can write PPS registers
    __builtin_write_OSCCONL(OSCCON & 0xBF);
   
    //Define PPS Outputs
    RPOR0bits.RP1R = 0b00111; //SDO1 Output - RP1R<4:0> = 00111 - RP1 (Pin 5)tied to SPI1 Data output
    RPOR1bits.RP2R = 0b01000; //SCK1 Output - RP2R<4:0> = 01000 - RP2 (Pin 6)tied to SPI1 Clock output
    //RPOR3bits.RP6R = 0b10010; // Pin 15 is Output Compare 1 PWM - Connect OC1 to RB8/RP40 (Pin 15 on the DIP)
    RPOR4bits.RP9R = 0b10010; // Pin 18 is Output Compare 1 PWM - Connect OC1 to RB9/RP9 (Pin 18 on the DIP)
        
    //Define PPS Inputs
        
    // Lock things up again
    __builtin_write_OSCCONL(OSCCON | 0x40);
    
    AD1PCFGL = 0xFFFF;
    AD1PCFGLbits.PCFG0 = 0; // AN0 as analog input
    AD1PCFGLbits.PCFG2 = 1; // AN0 as digital input
}

void pll_init()//Set up 16Mhz Crystal PLL for 80 MHz operation.
{
    CLKDIVbits.PLLPRE = 0; // (1) Divide by (PLLPRE+2)Default
    PLLFBDbits.PLLDIV = 38; // (2) Multiply by (PLLDIV+2)
    CLKDIVbits.PLLPOST = 0; // (3) Divide by 2*(PLLPOST+1) //
    while (OSCCONbits.LOCK != 1); // Wait for PLL to lock
    RCONbits.SWDTEN = 0; // Disable Watch Dog Timer
}

void spi_init(void)
{
    SPI1STATbits.SPIEN = 0;
    /*
    SPI1CON1bits.SPRE =0b111;//secondary prescale 1:1
    SPI1CON1bits.PPRE = 0b10;//primary prescale 4:1 - 10Mhz clock
    SPI1CON1bits.DISSCK = 0;
    SPI1CON1bits.DISSDO = 0;
    SPI1CON1bits.MODE16 = 1;
    SPI1CON1bits.CKE = 1;
    SPI1CON1bits.SSEN = 0;
    SPI1CON1bits.CKP = 0;
    SPI1CON1bits.MSTEN = 1;
    SPI1CON1bits.SMP = 0;
    */
    SPI1CON1 = 0b0000010100111110;
    SPI1STATbits.SPIEN = 1;
}

void timer2_init()//Timer 2: Used for DDS sine generation

{
    T2CONbits.TON = 0; // Enable Timer 2
    TMR2 = 0; // Clear TMR2
    PR2 = 255; // 255 gives stable interrupt 71.8Khz
    T2CONbits.T32 = 0; // 16 bit mode
    T2CONbits.TCKPS = 0; // Prescale 1:1
    IEC0bits.T2IE = 1; // Set Timer 2 interrupt enable bit
    T2CONbits.TON = 1; // Enable Timer 2
}

void timer3_init()//Timer 3: Used for triggering ADC conversion.

{
    TMR3 = 0x0000; // Clear TMR3
    PR3 = SAMPPRD; // Load period value in PR3
    IFS0bits.T3IF = 0; // Clear Timer 3 Interrupt Flag
    IEC0bits.T3IE = 1; // Clear Timer 3 interrupt enable bit
    T3CONbits.TON = 1; // Enable Timer 3
}


void __attribute__((interrupt, no_auto_psv)) _T2Interrupt(void)//interrupt on Timer2 rollover
{
   
const int sine[] =
{
    2048,2098,2149,2199,2249,2299,2349,2398,2448,2497,2546,2594,2643,2690,2738,2785,
    2832,2878,2924,2969,3013,3057,3101,3144,3186,3227,3268,3308,3347,3386,3423,3460,
    3496,3531,3565,3599,3631,3663,3693,3722,3751,3778,3805,3830,3854,3877,3899,3920,
    3940,3959,3976,3993,4008,4022,4035,4046,4057,4066,4074,4081,4086,4090,4094,4095,
    4096,4095,4094,4090,4086,4081,4074,4066,4057,4046,4035,4022,4008,3993,3976,3959,
    3940,3920,3899,3877,3854,3830,3805,3778,3751,3722,3693,3663,3631,3599,3565,3531,
    3496,3460,3423,3386,3347,3308,3268,3227,3186,3144,3101,3057,3013,2969,2924,2878,
    2832,2785,2738,2690,2643,2594,2546,2497,2448,2398,2349,2299,2249,2199,2149,2098,
    1998,1947,1897,1847,1797,1747,1698,1648,1599,1550,1502,1453,1406,1358,1311,1264,
    1218,1172,1127,1083,1039,995,952,910,869,828,788,749,710,673,636,600,
    565,531,497,465,433,403,374,345,318,291,266,242,219,197,176,156,
    137,120,103,88,74,61,50,39,30,22,15,10,6,2,1,0,
    1,2,6,10,15,22,30,39,50,61,74,88,103,120,137,156,
    176,197,219,242,266,291,318,345,374,403,433,465,497,531,565,600,
    636,673,710,749,788,828,869,910,952,995,1039,1083,1127,1172,1218,1264,
    1311,1358,1406,1453,1502,1550,1599,1648,1698,1747,1797,1847,1897,1947,1998,2048

 };

    phaseaccum = (phaseaccum + tuningword); // Add tuning word to accumulator
    
    if (phaseaccum <= tuningword) //phase accumulator has rolled over
       
        {
            mod_audio = (sine[sine_i]); //Value from sine table
            sine_i++; //Increment sine table counter
                        
            if (sine_i >= 255) //Wrap around sine table counter
                {
                    sine_i = 0;
                }
        }
         TP = !TP;
    
       IFS0bits.T2IF = 0; // Clear the Timer2 Interrupt Flag
}

void __attribute__((interrupt, auto_psv)) _T3Interrupt(void)//interrupt on Timer3 rollover -

{
__delay_us(2);
    
              
     cs=0; // Select DAC chip select
    SPI1BUF = (0b0011000000000000 |((mod_audio>>1) & 0b0000111111111111)); //Send Sine to DAC for testing
  
    while(SPI1STATbits.SPITBF);
    while (!SPI1STATbits.SPIRBF); // Wait for the dummy byte clocked in during the command write to appear
    dummy = SPI1BUF; //Avoiding overflow when reading
    cs = 1; // De-select DAC chip select
 IFS0bits.T3IF = 0; // Clear the Timer2 Interrupt Flag
}



  
 void modfreq_init( void )
{

 dipsw = ((8 * !JP4)+(4 * !JP3)+ (2 * !JP2) + !JP1); //Check switches
 
 if (dipsw == 0) modvalsel = 0; //Select frequency from table in while loop
 if (dipsw == 1) modvalsel = 1;
 if (dipsw == 2) modvalsel = 2;
 if (dipsw == 3) modvalsel = 3;
 if (dipsw == 4) modvalsel = 4;
 if (dipsw == 5) modvalsel = 5;
 if (dipsw == 6) modvalsel = 6;
 if (dipsw == 7) modvalsel = 7;
 if (dipsw == 8) modvalsel = 8;
 if (dipsw == 9) modvalsel = 9;
 if (dipsw == 10) modvalsel = 10;
 if (dipsw == 11) modvalsel = 11;
 if (dipsw == 12) modvalsel = 12;
 if (dipsw == 13) modvalsel = 13;
 if (dipsw == 14) modvalsel = 14;
 if (dipsw == 15) modvalsel = 15;

}

int main(void)

{
    
    Pin_Init();
    pll_init();
    spi_init();
    timer2_init();
    timer3_init();
   
    unsigned long modval [16];//Switch frequencies modval = tuningword = (modvalinc * desired frequency)
        
        modval [0] = (modvalinc * 12); //12Hz
        modval [1] = (modvalinc * 14.5);//14.5Hz
        modval [2] = (modvalinc * 20.3);//20.3Hz
        modval [3] = (modvalinc * 25.6);//25.6Hz
        modval [4] = (modvalinc * 28.7);//28.7Hz
        modval [5] = (modvalinc * 30);//30Hz
        modval [6] = (modvalinc * 32);//32Hz
        modval [7] = (modvalinc * 42.8);//42.8Hz
        modval [8] = (modvalinc * 50);//50Hz
        modval [9] = (modvalinc * 60);//60Hz
  modval [10] = (modvalinc * 70);//70Hz
  modval [11] = (modvalinc * 75);//80Hz
  modval [12] = (modvalinc * 80);//90Hz
  modval [13] = (modvalinc * 85);//100Hz
  modval [14] = (modvalinc * 90);//110Hz
  modval [15] = (modvalinc * 95);//Cyberman
    
    while (1)
        {
        modfreq_init();
        tuningword = modval[modvalsel]; //Frequency selected from list
        
    }
    

}

#1

23 Replies Related Threads

    mbrowning
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    Re: Ring modulator DDS sine generation whine in output from DAC MCP4822 2017/09/13 04:09:49 (permalink)
    0
    What is the sample rate and do you have a reconstruction filter at the dac output to filter it out?
    - never mind. I see it's 48khz in the code
    post edited by mbrowning - 2017/09/13 04:11:51

    Can't remember. I've slept since then - Mark
    #2
    Trackhappy
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    Re: Ring modulator DDS sine generation whine in output from DAC MCP4822 2017/09/13 04:24:03 (permalink)
    0
    Thanks Mark. yep 48Khz, which is also teh audio sampling rate. No filter on the DAC output. When I was using the internal DAC it didn't have this issue and it had no filter, so I followed suit with the external DAC. It seems less pronounced as the audio frequency increases (my range of interest for the modulating sine wave is 10Hz to 120Hz).
    As I said, with audio looped through, it sounds perfectly clear, the problem is with the sine generation it seems.
    Cheers,
    Glenn.
     
    #3
    CinziaG
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    Re: Ring modulator DDS sine generation whine in output from DAC MCP4822 2017/09/13 04:57:25 (permalink)
    0
    Also, use a switch() up there Smile

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    #4
    Trackhappy
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    Re: Ring modulator DDS sine generation whine in output from DAC MCP4822 2017/09/13 05:38:51 (permalink)
    4 (1)
    Thanks Cinzia. Will look into that. The eventual aim is to get skilled enough to sample a pot in between the audio samples and use that to set the modulation frequency. Sounds easy... ;)
     
    #5
    du00000001
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    Re: Ring modulator DDS sine generation whine in output from DAC MCP4822 2017/09/13 08:51:38 (permalink)
    3 (1)
    I do not have the time to go through the whole code. But I'm rather good in such questions Smile: Smile
    Would you please provide a summary of what you intend to do, especially ansering
    1. DAC update rate (48 kHz if I got it right) ?
    2. Frequency (range?) of the "carrier" you want to modulate ?
    3. Frequency (range) of the modulating signal (10 - 120 Hz - correct?) ?
    4. Resolution (no of bits) of the modulating signal ?
    5. What do you consider as "high-pitched" ? Frequency ? 
      Any chance you could measure the signal via some scope ?
    What else did I identify ?
    • The sine is defined with 12 Bits of resolution
     

    Most times the bug is in front of the keyboard.
    #6
    Trackhappy
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    Re: Ring modulator DDS sine generation whine in output from DAC MCP4822 2017/09/13 13:39:40 (permalink)
    3 (1)
    Hi D00000001,
     
    yep. 48Khz (probably way too high for my application, but it works).
    The carrier is voice, and the antialiasing filter cutoff is about 4Khz, so say 100Hz to 4Khz.
    10-120Hz is correct.
    The ADC sampling the voice is 12 bit.
    The external DAC is 10 bit.
    On the scope, all I see is a fairly reasonable (maybe slightly "ragged") sine wave. I can't isolate the problem signal but is sounds like something around 4Khz to my ear. 
    The generation is carried out in interrupt, so was wondering if maybe there is an issue there with priority or something. There is nothing else going on in this stripped down version, so it shouldn't be. WDT is off. I read something about interrupt lag causing issues but it didn't seem directly relevant to me. Not sure what else it might be, which is why I have come to the brains trust.
    The code is (I hope) well commented. I originally had a 12 bit signed sine table, and dropped it down to see if that helped. I do note that toggling a pin in the interrupt routine is not perfectly steady, there is a "side artefact" to the signal which might be some instability in the interrupt.
    Thanks,
    Glenn.
    #7
    CinziaG
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    Re: Ring modulator DDS sine generation whine in output from DAC MCP4822 2017/09/13 14:00:26 (permalink)
    0
    Making one (the most important) IRQ handler "shadow" might help jitter i.e. overhead. You may try...

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    #8
    du00000001
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    Re: Ring modulator DDS sine generation whine in output from DAC MCP4822 2017/09/13 14:09:48 (permalink)
    3 (1)
    Jitter shouldn't be an issue if the interrupt is at 48 kHz.
    What about the anti-aliasing filter: is this an external filter or are you sampling at 48 kHz - applying some digital filter?
    A "4 kHz whine" might correlate with some digital IIR filter.
     
    And did I get it right? You intend to modulate speech with these 10 .. 120 Hz?
    Some "strange voice" effect?

    Most times the bug is in front of the keyboard.
    #9
    Trackhappy
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    Re: Ring modulator DDS sine generation whine in output from DAC MCP4822 2017/09/13 15:18:53 (permalink)
    5 (1)
    If you have ever watched Dr Who, you might understand more ;) . The filter is analog, on the audio input before the ADC. As the code is presented here, the filter and ADC is not used, neither is the audio input path. This code simply generates a sine wave in digital form and outputs it to the DAC to become audio at the desired frequency. The DAC chip has been used for music reproduction in some projects I found online, so I don't think it is a limitation of the chip itself. I tried lowering the 48Khz right down to 8Khz in steps, the noise remains but drops in frequency. Going up in modulation frequency, the effect seems to diminish,  but that is pretty subjective. I wish I had the equipment and knowledge to isolate it and measure it.
     
    I'll check out shadow as well. Thanks for that. It might become more important when I reinstate the other two interrupt routines.
     
    post edited by Trackhappy - 2017/09/13 18:35:50
    #10
    rpg7
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    Re: Ring modulator DDS sine generation whine in output from DAC MCP4822 2017/09/14 08:13:18 (permalink)
    4.5 (2)
    The problem is most likely because in order to produce 25Hz, you have to output 10 samples of the same value and then change to the next value. This effectively drops your sample rate to 4.8kHz. So the best think to do would be to use an low pass filter with a cutoff of 1 to 2 kHz.
    #11
    mbrowning
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    Re: Ring modulator DDS sine generation whine in output from DAC MCP4822 2017/09/14 08:41:38 (permalink)
    4 (1)
    rpg is probably right. I threw this in excel. If the 10b DAC really goes from 0 to 1023, there are long periods at the high and low points of the sine wave where the output doesn't change for up to 10 samples (27 samples at min or max output). If the amplitude is less, then this problem is exacerbated.
    If this is a real problem and filtering can't fix it, you need more DAC bits or maybe a couple bits of dithering.

    Can't remember. I've slept since then - Mark
    #12
    rpg7
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    Re: Ring modulator DDS sine generation whine in output from DAC MCP4822 2017/09/14 10:28:39 (permalink)
    3 (1)
    mbrowning
    If the 10b DAC really goes from 0 to 1023, there are long periods at the high and low points of the sine wave where the output doesn't change for up to 10 samples (27 samples at min or max output). If the amplitude is less, then this problem is exacerbated.
    If this is a real problem and filtering can't fix it, you need more DAC bits or maybe a couple bits of dithering.

    The problem is that he is outputting a 25Hz wave at 48kHz. This is 1920 samples and he has a  table with 256 entries (he only uses 255) so on average every sample is repeated 7 or 8 times. so the steps occur around 6000 times per second. EVEN where the table changes value for every entry, not just at the top and bottom of the wave.
    #13
    mbrowning
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    Re: Ring modulator DDS sine generation whine in output from DAC MCP4822 2017/09/14 11:08:01 (permalink)
    3 (1)
    It's worse than I thought :) I was thinking theoretically and didn't really look at the implementation which basically creates it's own very large quantization noise.
    Linear interpolation between table points should work then, reducing the noise in the audible region and spreading it higher.

    Can't remember. I've slept since then - Mark
    #14
    Trackhappy
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    Re: Ring modulator DDS sine generation whine in output from DAC MCP4822 2017/09/14 13:32:36 (permalink)
    0
    Thank you all so much, That explanation makes sense to me, and 6Khz would pretty much be where my ears can hear the noise. Code to interpolate is probably beyond me at this point (will look around for examples), but given I am not short on memory would a simple test be to make my table 6 times the size?
     
    #15
    mbrowning
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    Re: Ring modulator DDS sine generation whine in output from DAC MCP4822 2017/09/14 13:35:43 (permalink)
    3 (1)
    If you've got the memory, a bigger table would seem the simplest improvement.

    Can't remember. I've slept since then - Mark
    #16
    du00000001
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    Re: Ring modulator DDS sine generation whine in output from DAC MCP4822 2017/09/14 13:57:16 (permalink)
    3 (1)
    OK - noise from the sine table (w/o interpolation) might explain the whine.
    While 1-Bit steps explain nothing - even not if they occur with 4.8 kHz. The reason for this is quite simple: too low an amplitude. (OK - he's got "only" 10 bits of DAC resolution . Anyway - this is too small to be heard. AND the steps are not evenly space: - more dispersed towards the sine extremes, denser during the zero transistions. No uniform frequency.)

    Most times the bug is in front of the keyboard.
    #17
    du00000001
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    Re: Ring modulator DDS sine generation whine in output from DAC MCP4822 2017/09/14 14:01:40 (permalink)
    3 (1)
    Code to interpolate is probably beyond me at this point (will look around for examples), but given I am not short on memory would a simple test be to make my table 6 times the size?

     
    Making the table 6 times the size might mask the basic problem (shifting the frequency towards the inaudible range) but would not solve it. Better to learn about interpolation, which is not too difficult.
     
    One link: http://www.codecogs.com/library/maths/approximation/interpolation/linear.php
    (More to find googling "linear interpolation c" (w/o the parentheses).

    Most times the bug is in front of the keyboard.
    #18
    Trackhappy
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    Re: Ring modulator DDS sine generation whine in output from DAC MCP4822 2017/09/14 20:48:02 (permalink)
    3 (1)
    Thanks. I will look into interpolation while I try a bigger table out of interest. The noise is not actually that bad in the full application so maybe a bigger table will be enough to get over the line.
     
    BTW, I made an error in my posting, not that it makes a difference but the MCP4822 is a 12 bit DAC, not 10.
    post edited by Trackhappy - 2017/09/14 22:22:12
    #19
    Trackhappy
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    Re: Ring modulator DDS sine generation whine in output from DAC MCP4822 2017/09/16 13:59:02 (permalink)
    3 (1)
    Thanks to everybody. I tried a sine table of 2048 values and it made surprisingly little difference. In the process, I had to change the rate I was sending samples (Timer 2). This exacerbated the strangeness with the interrupts.
    Even enabling Timer2 interrupt with nothing in the ISR caused the Timer3 ISR problems, which controlss the ADC. Instead of using an ISR for the Sine table, I am now just checking for the Timer2 counter to roll over and it seems to be behaving. I will look into interpolation as well, and try the shadow option to see if that fixes the interrupt issue. 
     
    #20
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