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1and0
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Re: Searching for information to program modern asm 2019/08/23 11:57:18 (permalink)
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I'm out of idea, unless there is more relocatable mode bugs. ;)  Try absolute mode?! 
#81
_pike
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Re: Searching for information to program modern asm 2019/08/23 13:44:04 (permalink)
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Replacing  LFSR FSR0 ,BUFFER   to

   MOVLW HIGH BUFFER
   MOVWF FSR0H
   MOVLW LOW BUFFER
   MOVWF FSR0L
 
it works...!!!! But i still have some questions to post later on....   Thank you!!!!!
 
 
<edit> So i come to conclude that LFSR instruction has this bug and cannot handle buffers that hold more than 160 bytes.. <edit>
 
post edited by _pike - 2019/08/23 13:46:40
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1and0
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Re: Searching for information to program modern asm 2019/08/23 14:10:41 (permalink)
+1 (1)
_pike
Replacing  LFSR FSR0 ,BUFFER   to

  MOVLW HIGH BUFFER
  MOVWF FSR0H
  MOVLW LOW BUFFER
  MOVWF FSR0L
 
it works...!!!!

That is what my macro does.
 

<edit> So i come to conclude that LFSR instruction has this bug and cannot handle buffers that hold more than 160 bytes.. <edit>

I played with it a bit just now. When your buffer is 160 or less bytes, the linker allocates it to Bank 0; when it is more than 160 bytes, it is allocated to a higher bank. So it seems when the buffer is allocated to a bank other than Bank 0, the LFSR instruction does not work correctly. :(
 
Also, when I forced the buffer to a bank other than Bank 0, LFSR does not work correctly.
 
<edit> It is 160 bytes because Bank 0 in your PIC18 K42 has only 160 non-access-RAM bytes.
 
My conclusion: When in relocatable mode, LFSR does _not_ work when it is pointing to a bank other than Bank 0.  This is an MPASM assembler MPLINK linker bug, which Microchip should have fixed one year ago.
 
 
 
 
post edited by 1and0 - 2019/08/23 14:51:56
#83
NorthGuy
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Re: Searching for information to program modern asm 2019/08/23 14:43:44 (permalink)
+1 (1)
1and0
My conclusion: When in relocatable mode, LFSR does _not_ work when it is pointing to a bank other than Bank 0.  This is an MPASM assembler bug, which Microchip should have fixed one year ago.



I think it's a linker bug. That's why it works in absolute mode where relocations are not involved.
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Re: Searching for information to program modern asm 2019/08/23 14:50:14 (permalink)
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NorthGuy
 
I think it's a linker bug. That's why it works in absolute mode where relocations are not involved.

Of course, it is the linker, not the assembler.  It's been a long day!
 
And I have found a pattern to the bug, where Bank is from a relocatable symbol.
 
Bank FSR0H
0x00 0x00
0x01 0x04
0x02 0x08
0x03 0x0C
0x04 0x10
0x05 0x14
0x06 0x18
0x07 0x1C

0x08 0x20
0x09 0x24
0x0A 0x28
0x0B 0x2C
0x0C 0x30
0x0D 0x34
0x0E 0x38
0x0F 0x3C

0x10 0x00
0x11 0x04
0x12 0x08
0x13 0x0C
0x14 0x10
0x15 0x14
0x16 0x18
0x17 0x1C

0x18 0x20
0x19 0x24
0x1A 0x28
0x1B 0x2C
0x1C 0x30
0x1D 0x34
0x1E 0x38
0x1F 0x3C
 
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1and0
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Re: Searching for information to program modern asm 2019/08/23 15:21:48 (permalink) ☄ Helpfulby _pike 2019/08/25 04:25:33
+1 (1)
_pike
Replacing  LFSR FSR0 ,BUFFER   to

  MOVLW HIGH BUFFER
  MOVWF FSR0H
  MOVLW LOW BUFFER
  MOVWF FSR0L
 
it works...!!!! 

If that works, then your code in Post #80 using my macro should work too. But you said it does not work ???
 
 
 
Edit:  Replace this

    lfsrX    FSR0,BUFFER  ; load pointer
        movf    index,w      ; get index
        movwf   FSR0L
        movffl  U1RXB,INDF0  ; store into buffer[index]
        incf    index        ; increment index
        retfie  FAST

with this

        movlw   high BUFFER  ; load pointer
        movwf   FSR0H
        movf    index,w      ; get index
        movwf   FSR0L
        movffl  U1RXB,INDF0  ; store into buffer[index]
        incf    index        ; increment index
        retfie  FAST

to shave two words off. ;)
post edited by 1and0 - 2019/08/23 15:34:04
#86
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Re: Searching for information to program modern asm 2019/08/25 04:33:38 (permalink)
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1and0
NorthGuy
 
I think it's a linker bug. That's why it works in absolute mode where relocations are not involved.

Of course, it is the linker, not the assembler.  It's been a long day!
 
And I have found a pattern to the bug, where Bank is from a relocatable symbol.
 
Bank FSR0H
0x00 0x00
0x01 0x04
0x02 0x08
0x03 0x0C
0x04 0x10
0x05 0x14
0x06 0x18
0x07 0x1C

0x08 0x20
0x09 0x24
0x0A 0x28
0x0B 0x2C
0x0C 0x30
0x0D 0x34
0x0E 0x38
0x0F 0x3C

0x10 0x00
0x11 0x04
0x12 0x08
0x13 0x0C
0x14 0x10
0x15 0x14
0x16 0x18
0x17 0x1C

0x18 0x20
0x19 0x24
0x1A 0x28
0x1B 0x2C
0x1C 0x30
0x1D 0x34
0x1E 0x38
0x1F 0x3C
 


 Microchip should thank you !!!  I read in a different thread that you open something like a ticket where you report bugs.... Is it possible to inform them so to fix it since you are an experienced one? Also the bug you say is on the 0x10 0x00 where it supposed to be 0x10 0x40 ?
Finally the code i said it worked it was with the initial source without having it modified by your macro i will use the new one that you have posted and i will tell you the results.... Smile: Smile
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Re: Searching for information to program modern asm 2019/08/25 10:19:56 (permalink)
+1 (1)
_pike
 
 
Microchip should thank you !!!  I read in a different thread that you open something like a ticket where you report bugs.... Is it possible to inform them so to fix it since you are an experienced one?

Anyone can submit a ticket to Microchip. From the link I posted earlier, it seems someone has already submitted a ticket to Microchip over a year ago on this bug. One year later and it still has not been fixed; somehow I'm not surprised. :(
 

Also the bug you say is on the 0x10 0x00 where it supposed to be 0x10 0x40 ?

No. The bug here with LFSR in relocatable mode is it links the wrong bank (except Bank 0) to the high byte FSRxH, as shown in my previous post.
 
#88
cea
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Re: Searching for information to program modern asm 2019/08/25 18:13:46 (permalink)
+1 (1)
This LFSR issue with MPLINK has been discussed in the forum since 2018.
 
I have open another case about this (#00455087).
 
This is the source code I sent them:
 LIST N=0,C=255,R=DEC
;*******************************************************************************
;                                                                              *
;    Filename: main.asm                                                        *
;    Date: 8-25-2019  17:00:52                                                 *
;    Author:                                                                   *
;    Target: PIC18LF27K42                                                      *
;    Compiler: MPASMWIN v5.84                                                  *
;    IDE: MPLABX v5.25                                                         *
;    Description: Test LFSR behavior, relocatable vs absolute                  *
;                                                                              *
;    BUG: Why does the MPLINK (v5.09) load the wrong address when the buffer   *
;         is a relocatable objec even when the address of the RAM location     *
;         has been specified at the time of build?                             *
;                                                                              *
;    NOTE: This bug was reported in MPASMWIN v5.81 on or about August 20, 2018 *
;     See:  https://www.microchip.com/forums/FindPost/1065026                  *
;     Also: https://www.microchip.com/forums/FindPost/1109818                  *
;     Also: https://www.microchip.com/forums/FindPost/1102630                  *
;     Also: https://www.microchip.com/forums/FindPost/1064775                  *
;                                                                              *
;*******************************************************************************

#include "p18lf27k42.inc"

; CONFIG1L
  CONFIG  FEXTOSC = OFF         ; External Oscillator Selection (Oscillator not enabled)
  CONFIG  RSTOSC = HFINTOSC_64MHZ; Reset Oscillator Selection (HFINTOSC with HFFRQ = 64 MHz and CDIV = 1:1)

; CONFIG1H
  CONFIG  CLKOUTEN = OFF        ; Clock out Enable bit (CLKOUT function is disabled)
  CONFIG  PR1WAY = OFF          ; PRLOCKED One-Way Set Enable bit (PRLOCK bit can be set and cleared repeatedly)
  CONFIG  CSWEN = ON            ; Clock Switch Enable bit (Writing to NOSC and NDIV is allowed)
  CONFIG  FCMEN = OFF           ; Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)

; CONFIG2L
  CONFIG  MCLRE = EXTMCLR       ; MCLR Enable bit (If LVP = 0, MCLR pin is MCLR; If LVP = 1, RE3 pin function is MCLR )
  CONFIG  PWRTS = PWRT_OFF      ; Power-up timer selection bits (PWRT is disabled)
  CONFIG  MVECEN = ON           ; Multi-vector enable bit (Multi-vector enabled, Vector table used for interrupts)
  CONFIG  IVT1WAY = OFF         ; IVTLOCK bit One-way set enable bit (IVTLOCK bit can be cleared and set repeatedly)
  CONFIG  LPBOREN = OFF         ; Low Power BOR Enable bit (ULPBOR disabled)
  CONFIG  BOREN = SBORDIS       ; Brown-out Reset Enable bits (Brown-out Reset enabled , SBOREN bit is ignored)

; CONFIG2H
  CONFIG  BORV = VBOR_190       ; Brown-out Reset Voltage Selection bits (Brown-out Reset Voltage (VBOR) set to 1.90V)
  CONFIG  ZCD = OFF             ; ZCD Disable bit (ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON)
  CONFIG  PPS1WAY = OFF         ; PPSLOCK bit One-Way Set Enable bit (PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence))
  CONFIG  STVREN = ON           ; Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
  CONFIG  DEBUG = OFF           ; Debugger Enable bit (Background debugger disabled)
  CONFIG  XINST = OFF           ; Extended Instruction Set Enable bit (Extended Instruction Set and Indexed Addressing Mode disabled)

; CONFIG3L
  CONFIG  WDTCPS = WDTCPS_31    ; WDT Period selection bits (Divider ratio 1:65536; software control of WDTPS)
  CONFIG  WDTE = OFF            ; WDT operating mode (WDT Disabled; SWDTEN is ignored)

; CONFIG3H
  CONFIG  WDTCWS = WDTCWS_7     ; WDT Window Select bits (window always open (100%); software control; keyed access not required)
  CONFIG  WDTCCS = SC           ; WDT input clock selector (Software Control)

; CONFIG4L
  CONFIG  BBSIZE = BBSIZE_512   ; Boot Block Size selection bits (Boot Block size is 512 words)
  CONFIG  BBEN = OFF            ; Boot Block enable bit (Boot block disabled)
  CONFIG  SAFEN = OFF           ; Storage Area Flash enable bit (SAF disabled)
  CONFIG  WRTAPP = OFF          ; Application Block write protection bit (Application Block not write protected)

; CONFIG4H
  CONFIG  WRTB = OFF            ; Configuration Register Write Protection bit (Configuration registers (300000-30000Bh) not write-protected)
  CONFIG  WRTC = OFF            ; Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
  CONFIG  WRTD = OFF            ; Data EEPROM Write Protection bit (Data EEPROM not write-protected)
  CONFIG  WRTSAF = OFF          ; SAF Write protection bit (SAF not Write Protected)
  CONFIG  LVP = ON              ; Low Voltage Programming Enable bit (Low voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored)

; CONFIG5L
  CONFIG  CP = OFF              ; PFM and Data EEPROM Code Protection bit (PFM and Data EEPROM code protection disabled)

;*******************************************************************************
; Declare RAM buffers
;*******************************************************************************
 
BUFFER0 UDATA   0x001d00
Buf0:   RES     .256
BUFFER1 UDATA   0x001e00
Buf1:   RES     .256
BUFFER2 UDATA   0x001f00
Buf2:   RES     .256

  cblock 0x001d00
    aBuf0:.256
  endc
 
  cblock 0x001e00
    aBuf1:.256
  endc
 
  cblock 0x001f00
    aBuf2:.256
  endc

;*******************************************************************************
; Reset Vector
;*******************************************************************************

RES_VECT  CODE   0x0000             ; processor reset vector
    GOTO    START                   ; go to beginning of program

ISRHV     CODE    0x0008
    GOTO    HIGH_ISR
ISRLV     CODE    0x0018
    GOTO    LOW_ISR

;*******************************************************************************
; MAIN PROGRAM
;*******************************************************************************

MAIN_PROG CODE                      ; let linker place main program
 
HIGH_ISR
;     <Insert High Priority ISR Here - no SW context saving>
    RETFIE  FAST
;
LOW_ISR
;       <Search the device datasheet for 'context' and copy interrupt
;       context saving code here>
    RETFIE

START
    LFSR    FSR0,Buf0
    LFSR    FSR0,aBuf0
    LFSR    FSR1,Buf1
    LFSR    FSR1,aBuf1
    LFSR    FSR2,Buf2
    LFSR    FSR2,aBuf2
    GOTO $                          ; loop forever

    END

 
This is the disassembly of that code I sent them:
      Line     Address      Opcode      Label                   DisAssy
                                                 Application Partition
    2       00000        EF10                  GOTO 0x20
    3       00002        F000                  NOP
    4       00004        0000                  NOP
    5       00006        FFFF                  NOP
    6       00008        EF0E                  GOTO 0x1C
    7       0000A        F000                  NOP
    8       0000C        FFFF                  NOP
    9       0000E        FFFF                  NOP
    10      00010        FFFF                  NOP
    11      00012        FFFF                  NOP
    12      00014        FFFF                  NOP
    13      00016        FFFF                  NOP
    14      00018        EF0F                  GOTO 0x1E
    15      0001A        F000                  NOP
    16      0001C        0011                  RETFIE 1
    17      0001E        0010                  RETFIE 0
    18      00020        EE0D                  LFSR 0, 0x3400
    19      00022        F000                  NOP
    20      00024        EE07                  LFSR 0, 0x1D00
    21      00026        F100                  NOP
    22      00028        EE1E                  LFSR 1, 0x3800
    23      0002A        F000                  NOP
    24      0002C        EE17                  LFSR 1, 0x1E00
    25      0002E        F200                  NOP
    26      00030        EE2F                  LFSR 2, 0x3C00
    27      00032        F000                  NOP
    28      00034        EE27                  LFSR 2, 0x1F00
    29      00036        F300                  NOP
    30      00038        EF1C                  GOTO 0x38
    31      0003A        F000                  NOP

 
I have had some experience with this process in the past so I do not have high hopes of a timely response.
#89
cea
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Re: Searching for information to program modern asm 2019/08/28 12:28:23 (permalink)
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Microchip has responded to my case with this:
 
Microchip Support
We are aware of the issue and the reference number for the issue MPASM-475.
I have requested the Development team to fix this issue.

 
There is no suggested work around.
There is no estimate of when a fix can be released.
 
My conclusion is to avoid updating a legacy 8-bit PIC project. When forced then design out the Microchip controller in favor of an ST, NXP, TI or any other 8-bit controller.
 
post edited by cea - 2019/08/28 12:30:30
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