The delay at the start of the I2C sequence is to avoid: The I2C sequence set is driven through interrupt. Any delay within the sequence will block the interrupt and thus any other thread as well. If a delay is required between two I2C component addresses, It should be really small (few us). usually this is not required anyway.
setting the I2C block sampling time to 0.01 second will provide a delay of 0.01s - the I2C transfert time.
With EEPROM write, please ensure that your are not overstressing the EEPROM max number of writing. The I2C block writting to the EEPROM might probably be in a conditionally executed subsystem.
The I2C block propose an additional output which let you know if the sequence executed completely, receiving all required ACK from the addresse component. You might check this output.
If you have a scope, please check the I2C lines to check the transaction. Maybe the problem is how the EEPROM is addressed as mentionned by Ric above.