I've found DS70005213G so I'll try to figure it out for myself but the configuration options in MCC appear to make no sense at all, I have a choice of:
AUX VCO DIVMUX
Now since the PLL is running at 1200MHz VCO/4 ought to be 300MHz, and I believe I probably need 50MHz (Tcy 20ns) to be confident of meeting the TADCORE > 14.3 nS [sic] I'd also add that I'm using FRC not FOSC as master clock.
bit 15-14 CLKSEL[1:0]: ADC Module Clock Source Selection bits(1)
11 = FVCO/4
10 = AFVCODIV
01 = FOSC
00 = FP (FOSC/2)
and a divider dividing by up to 64
1: The ADC input clock frequency, selected by the CLKSEL[1:0] bits, must not exceed 560 MHz.
2: The ADC clock frequency, after the first divider selected by the CLKDIV[5:0] bits, must not exceed
By comparison the documentation gives the sources as:
with the option of a programmable division set by 6 bits which doesn't seem to be mentioned in MCC "simple" view.