2020/11/13 03:37:44
Eusuvi
I'm connecting 8 mcp chips to the same SPI bus where the master node is a Raspberry Pi3.
 
1. I'm trying to check whether some of the lines would need a driver or not, between master line and slave, but I don't see information about current parameters on datasheet. I would like to check if a master SPI driver can give enough current to the slave. I guess that if there are 8 SPI nodes receiving hardware address data frame by MOSI, the MCPs will read and process the bytes at MOSI pin. So I should multiplicate per 8 the CLOCK, CS and MOSI lines current consumption. 
 
2. I have a second question regarding MCP chip SPI bus, whereas devices put the MISO line at high impedance when CS is high, what happening with the CS, SCLK and MOSI pins? How the MCP SPI driver handle the inputs when CS is high? Are also the rest of the lines put in high Z when the driver reads a low level at CS pin? 
 
Thanks for your attention.
2020/11/13 04:26:15
oliverb
The inputs should present negligible DC loading, so the limitation is probably a mix of total capacitance and cable/trace length. This tends to manifest as overshoots and ringing that can cause extra clock transitions, so the clock tends to be the first signal to give trouble. You may find you need a small resistance (try 100 ohm) in series with each output to damp this down.
 
If you do need to buffer the lines then at the PI end the buffers can be always enabled, and the MCP23S17 parts probably won't need buffering, they should have enough drive anyway.
 
2020/11/13 08:00:26
marcov
One tip: Read the errata about the "id" pins.
2020/11/14 02:22:51
oliverb
That reminds me: You'll probably find it easier to code the initialization if you implement a reset line. It means using up another GPIO line but you don't have to deal with having the parts in an uncertain state at program start.
 
OK so I don't follow my own advice instead I just tie reset high, but then I have to issue extra IOCON writes to deal with the uncertainty.
2020/11/16 01:11:30
Eusuvi
@oliverb and company, thanks for your reply. Your suggestions are useful and I understand what you mean. But I'm trying to know if I would need a buffer. That's the thing I don't know and I'm wondering. I suspect that if Rasp gives 16mA for output pins and so it writes things towards 8 MCP devices I should multiply one chip line consumption x 8 chips. As I don't know what is the current value that a bus line pinat MCP is demanding, I don't know if master maximum driver current (16mA) will be enough for 8 devices reading the address frame at the same time.
 
Do you understand me what I mean?
2020/11/16 01:13:08
ric
Eusuvi
Do you understand me what I mean?

Yes, they did, and they already said the input current is negligible.
 
2020/11/16 01:54:00
marcov
I second oliverb's remark btw, for us a reset line was really needed to reliable init the s17s.
 
We had some other S17 initialization troubles, but in the end that was due to putting CS high too fast after SPI writes ended. Inserted some nops and it has been fine ever after.
2020/11/16 04:26:59
oliverb
Regarding device loads I know it is a bit strange. I was first taught TTL logic, and I remember one demonstration board using 1k pull-down resistors!! I've seen the current requirement put at 1.6mA.
 
Most logic ICs and ASICs are made in MOS technology, CMOS or NMOS, meaning that the active devices are "Field effect transistors" which are activated by voltage not current. The input to a CMOS device is a small capacitance. I couldn't find a figure for the MCP23S17 but an ordinary logic gate might have a capacitance of around 5pF. One exception is if there is an unpowered logic device on a bus. There is an internal diode between each logic pin and the positive supply pin (usually, exceptions exists) so an unpowered device will attempt to "steal" power from the bus. This is bad and can be destructive. Try not to let it happen.
 
The result of that is is takes negligible power to maintain the state of the bus, it only takes power to switch it, and the power is used to charge and discharge the capacitance of the inputs and of the traces leading to them. How much power depends on how far the signals need to go and how fast they need to be.
 
 
 
2020/11/16 04:40:26
Mysil
Hi, Eusuvi
 
Since you are asking again, it may seem you do not understand explaination above.
The Input in complementary metal–oxide–semiconductors as used in microcontrollers,
computer chps, and MCP23S17 port expanders,
is just a small pad of metal, on top of a layer of silicon oxide, which is basically a kind of glass.
 
These inputs use no current when the signal is stable.
The input act as a very small capacitor.  Bonding wire, together with connection pad and traces inside the chip package and pin of the package, also contribute with a little capacitance.
Together, these are sometimes estimated to 5 picoFarad or less for each input pin.
Traces on your circuit board, and other wiring between devices, may contribute much more capacitance,
especially if there is long wiring between devices.
Twisted pair wiring as used in Cat5e Ethernet cable, is specified to have nominally 52 pF/meter capacitance.
So signaling quality depend much more upon length and layout of wiring and connections,
than number of devices connected. And frequency of signaling.
 
You may calculate rise and fall times of signals when capacitance of the whole connect,
and other properties are known.
You may calculate signal propagation based on transmission line theory,
Or you may observe the signals using oscilloscope.
How long time does it take for signals at the far end of the setup to reach stable level,
and for eventual reflections and overshoot to decay.
 
Inputs of microcontrollers and computer chips are sensitive to EMC and EMI interference,
so if there are long wiring, signal transcievers may still be a good idea.
 
    Mysil
2020/11/16 04:58:27
oliverb
Another GOOD reason to add transcievers is that the PI has 3.3V outputs, and it is quite likely that you intend to run the MCP23S17 parts from 5V. There are rules for safely mixing 3.3V and 5V parts in the same system, but adding a level-translator may be simpler.
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