I need a 4MHz clock output on a PIC18F66K80 design I'm doing, and I'd like to get it from the PIC18F instead of setting up separate clock hardware. The PIC18F is already running from a 16MHz clock with its PLL enabled, so Fosc/4 internally is running at 16MHz and all I need to do is divide by 4 and emit the result.
Dividing down the clock and emitting it from a pin is a very common thing to do, and the CCP modules seem perfect for this. I've used them for dozens of other things and they've always impressed me with their flexibility. But I've never tried to generate a downsampled clock with them before, and I'm starting to believe it's not possible.
The (E)CCPx pin can be an output in Compare mode. However, it appears that one, and only
one, Compare mode clears the associated Timer and this gives you a programmable period: Special Event Trigger (SET) mode. And it does not appear that SET mode controls the output pin.
I first tried this on a couple of standard CCP modules, without success. I also tried it on the ECCP1 module in case its "enhanced" operation supported this - no luck.
The very clear block diagrams in the spec sheet VERY STRONGLY suggest that the CCP modules can control their output pins in any
Compare mode. However, it's looking like the only Compare modes that actually control the output pin are 0x02 (toggle output on match), 0x08 (init low, go high on match), and 0x09 (init high, go low on match). Testing reveals:
* Compare mode 0x02 (toggle on match) generates a 50% duty cycle output but always at TimerClock/64K regardless of the value written into the CCP's Period register. I suspect this is because this mode does not clear the associated Timer, so the Timer just free-runs and a match occurs once per overflow.
* Compare modes 0x08 and 0x09 (init one way, go the other on match) do indeed init properly, and then they flip the pin one time where it stays forever. I suspect what's happening is the Timer upcounts to the Period value, a match occurs so the pin is flipped, but then the pin just stays there because the Timer and pin aren't cleared to yield repeating action.
So what is needed is a Compare mode which both controls the pin (which 0x02, 0x08, and 0x09 do) and clears the Timer (which 0x0B SET mode does). Unfortunately, testing shows that 0x0B SET mode does not control the pin (though the block diagrams do not indicate this) and the other three Compare modes do not clear the Timer.
Is there some magic trick I'm missing here? Dividing down the clock and emitting it from a pin is a very common thing to do so you can share a single crystal-based clock in the system. It's hard to believe the otherwise super-flexible CCP's cannot do this.