2020/05/26 20:38:59
Hi everyone,
I have a I2C Bus with one master and several slaves, and 24LC64 is one of the slaves.
For some reasons, master would send out unexpected control byte accidentally.
Meaning the master is expected to send out a write byte to 0x48 ( S/0x48/W ), but instead, a read byte to 0x51 ( S/0x51/R ) is send out, which is the slave address of 24LC64.
Send a read byte directly to 24LC64 without a write byte, will cause 24LC64 to lock up I2C Bus, and thus no I2C communication can be performed.
My question is " How to make 24LC64 to release  I2C Bus from this situation? "
Thanks for your time, looking forward to any reply.
2020/09/11 16:49:50
Hi Adam,
Not difficult, look for the "I2C Software Reset Sequence", this is shown in AN1028 and several of the I2C EEPROM datasheets.  The trick to get the I2C slave to release the bus is to keep sending it clocks until it either sends a 1, or until it ends its transmission cycle.  Once we get a clear SDA line, we can send a STOP command which will clear the slave devices.  Sometimes they just show it as sending 9 clock ticks to clear the line, then a STOP, but the idea is still the same.  Give that a try to see if it works.
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