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Visit Microchip Technology at RISC-V Summit 2019

Microchip is excited to announce our participation at RISC-V Summit, December 9-12, 2019, at the San Jose Convention Center in San Jose, CA. The second annual RISC-V Summit will bring together developers, tool providers and silicon vendors to experience RISC-V technology. Join us in Booth #205 to meet with our experts and discuss how to create smart, connected and secure designs. You can expect to see the latest innovations from Microchip and our partners.

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Attend Ted Speers’ Keynote

Open for Business: True Stories of How Far We’ve Come With the RISC-V Ecosystem

Tuesday, December 10th at 10:20 a.m.

There can be no doubt that RISC-V has moved out of academia and is well into its commercialization and broad adoption phase. RISC-V has been making headlines around the world as startups to multibillion-dollar technology leaders have announced architectures and product families enabled by the free and open-source ISA. None of this would be possible without the establishment of a robust RISC-V ecosystem that fosters collaboration, innovation and enablement for the design community to build inventive hardware with RISC-V as its core. In this year’s keynote address, Microchip fellow and founding RISC-V board member Ted Speers will dive into “Collaborate, Innovate, Build It” by providing his insights on the exponential growth of the RISC-V ecosystem based on his own experiences in bringing about RISC-V-based products.

 

Speaker Biographies

bobmartin

Ted Speers is head of product planning for the FPGA business unit at Microchip, where he is responsible for defining its roadmap for low-power, secure and reliable FPGAs and SoC FPGAs. He joined Microsemi, now part of Microchip, in 1987 and held roles in process engineering and product engineering before assuming his current role in 2003. He is a Technical Fellow and co-inventor on 35 U.S. patents. Prior to joining Microsemi, he worked at LSI Logic. Ted has a Bachelor of Science degree in chemical engineering from Cornell. He is a founding member of the RISC-V Board of Directors.

 

Explore Our Partner Demos

Future-Proof Authentication and Identification Security for Critical PolarFire® SoC FPGA Applications

This demo features SecureRF’s digital signature verification method plus key agreement protocol running on the same processor used on the PolarFire SoC FPGA. These quantum-resistant cryptographic primitives enable developers to implement critical security functions such as secure boot, secure firmware update, remote device authentication, data integrity, data confidentiality and more. The demo highlights SecureRF’s performance advantage by comparing the runtime of its security protocol and algorithm with equivalent Elliptic Curve Cryptography (ECC) methods, ECDSA and ECDH.

Enabling IoT on Edge and Device

This demo showcases devices running the Nucleus® Real-Time Operating System (RTOS) that are connected to the cloud using Mentor® Embedded IoT Framework (MEIF) to an implement an IoT solution.

Creepy Teddy Grows Up

At last year’s Summit, Creepy Teddy showed you his machine learning skills. He's had a year to brush up on his skills and even learn a few tricks. Come by and say hello to Creepy Teddy.

AdaCore + Hex Five

This demo will show an Ada application using AdaCore’s GNATPro toolsuite running inside the Hex Five MultiZone™ nanokernel on SiFive’s RISC-V HiFive Unleashed board. The application will control a robotic arm and take command and control information from other zones using Hex Five’s InterZone™ Secure Communications channels.

Hex Five

MultiZone Security is the first Linux® enclave for RISC-V. The MultiZone demo shows you how to secure the deterministic behavior of mixed-criticality systems where Linux and real-time come together in a single PolarFire FPGA. For safety-critical applications that require trusted workloads on untrusted platforms, MultiZone Security provides software-defined, hardware-enforced separation for multiple enclaves, with full isolation of data, programs and peripherals. Contrary to legacy-thick hypervisor solutions, MultiZone is completely self-contained. It presents

an extremely limited attack surface (<2 KB), it is formally verifiable, and it doesn’t require changes to existing software. MultiZone PolarFire FPGA edition enables open-source software, third-party binaries and legacy code to be configured in minutes to achieve unprecedented levels of safety and security.

wolfSSL

wolfSSL will be demonstrating the performance of the industry-leading wolfCrypt and wolfSSL libraries on the HiFive Unleashed board. The demo will show live benchmarks, and technical personnel will be on hand to answer any questions.

Low-Power Thermal Imaging with Digital Core Technologies

Digital Core Technologies will be demonstrating a termal imaging solution. The demo uses a ULIS 64 × 480 thermal image sensor, Digital Core’s image pre-processing IP and embedded software on the PolarFire SoC FPGA pre-silicon development platform.