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8-Bit MCUs

Hardware Limit Timer (HLT)

The Hardware Limit Timer (HLT) provides a timed hardware limit to be used in conjunction with asynchronous analog feedback applications, or to detect missed periodic events.


  • Hardware monitoring for missed periodic events and fault detection (stalls, stops, etc.)
  • Period timer with external reset input
  • Flexible design
    • Selectable start of event trigger
    • Multiple modes
    • Seven available clock sources
  • Resolution of ¼ instruction cycle
  • Useable as a general purpose 8-bit timer/counter with external reset capabilities


  • Reduces code complexity
    • No code for detection set-up
    • No code to manage timer
  • Core independent operation
  • Operation while in low power SLEEP
hardware limit timer diagram