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16-bit Architecture

High-Performance CPU

  • 16-bit wide data path
  • 76 base instructions: mostly 1 word/1 cycle
  • 16, 16-bit general purpose registers
  • 16 x 16 signed fractional/integer multiplier
  • 32/16 and 16/16 divide
  • 40-stage barrel shifter
  • Up to 15 DMA channels between RAM and peripherals

Additional dsPIC DSC Performance

  • 8 base DSP instructions
  • Two 40-bit accumulators with rounding and saturation options
  • Single core combines MCU and DSP features
  • Adds Modulo and Bit-reverse address mode

Interrupt Controller

  • 5 cycle fixed latency
  • Up to 118 interrupt sources, up to 5 external
  • 7 programmable priority levels
  • 4 processor exceptions and software traps
  • Vectored interrupts

Compare 16-bit PIC® MCU Architectures

All of the following PIC24 MCU and dsPIC DSC families share common architecture, peripherals, pin-outs and development tools for easy scalability and migration.

Lowest Power
Higher Performance
Highest Performance MCU
High Performance DSC
Highest Performance DSC
Performance16 MIPS40 MIPS70 MIPS30 MIPS + DSP40 MIPS + DSP70 MIPS + DSP
Flash4K to 1024K12K to 256K32K to 512K6K to 144K12K to 256K32K to 512K
RAM512 to 96K1K to 16K8K to 52K256 to 8K1K to 30K8K to 52K

To learn more about the PIC24 MCU or dsPIC DSC core and peripherals, please view:

Family Reference Manuals

16-bit Video Channel