Modelling of LIN-Transceiver  ATA666x in VHDL-AMS
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Revision:	$Rev: 0 $
Last Update:	$Date: 2007-12-05 13:00:00 +0100 (Wed, 05 Dec 2007) $


Schematics
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lin_ata666x_tb.vhd		Testbench ATA 666x
lin_ata666x_tb_6662_6663.vhd	Testbench to compare ATA 6662 & ATA 6663

lin_ata666x_tb_7_18.vhd		Testbench 2xATA666x: 7.3V + 18V, 1k, 1nF
lin_ata666x_tb_vary.vhd		Testbench 3xATA666x: "typ" + "min" + "max", 7.3V,1k,1n

lin_ata666x_tb_A.vhd		Testbench like in Cadence
lin_ata666x_tb_B.vhd		Testbench Local wake-up request
lin_ata666x_tb_C.vhd		Testbench Wake-up via LIN (Remote wake-up request)
lin_ata666x_tb_D.vhd		Testbench 3xATA666x: "typ" + "min" + "max", 7.3V,1k,1n
lin_ata666x_tb_E.vhd		Testbench TXD time-out function of ATA6662, ATA6663 & ATA6664
lin_ata666x_tb_F.vhd		Testbench Wake-up via floating LIN (ATA6662 & ATA6663)
lin_ata666x_tb_G.vhd		Testbench current consumption of ATA666x

lin_ata666x.vhd			Top Level ATA666x
lin_core.vhd			LIN Core ATA666x


Start of simulation
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AdvanceMS

All simulations are prepared as batch run with .cmd and .do files.
Before running a testbench the models have to be compiled (tb_translate).

run_translate			Create library, compile models

run_tb				Compile and simulate lin_ata666x_tb.vhd
run_tb_6662_6663		Compile and simulate lin_ata6663_tb.vhd
run_tb_7_18			Compile and simulate lin_ata666x_tb_7_18.vhd
run_tb_vary			Compile and simulate lin_ata666x_tb_vary.vhd
run_tb_A			Compile and simulate lin_ata666x_tb_A.vhd
run_tb_B			Compile and simulate lin_ata666x_tb_B.vhd
run_tb_C			Compile and simulate lin_ata666x_tb_C.vhd
run_tb_D			Compile and simulate lin_ata666x_tb_D.vhd
run_tb_E			Compile and simulate lin_ata666x_tb_E.vhd
run_tb_F			Compile and simulate lin_ata666x_tb_F.vhd
run_tb_G			Compile and simulate lin_ata666x_tb_G.vhd

purge				Remove every created file (sources will NOT be touched)
