Register Access

Registers

The radio transceiver has a set of registers, which is used for configuration, reading status information and initiating transactions. All accessable registers are listed in the AT86RF230 data sheet.

• The radio transceiver configuration includes parameters like the current radio channel, the transmit power and the RX_AACK address filter parameters.
• The status information inludes the current radio transceiver status or the result of a TX_ARET transaction.
• With the term transaction, a frame transmission or reception in basic or extended operating mode as well as a CCA or energy measurement is denoted.

All registers in the AT86RF230 are 8 bit wide and they can be accessed with a single SPI command (see AT86RF230 data sheet) which is implemented in the functions trx_reg_read and trx_reg_write. The RG_<XYZ> macros contain the addresses of all registers.

Sub Registers

A sub register is a single bit or a group of adjacent bits within an 8 bit register. It represent a logical value in the radio transceiver, e.g. a power level, a channel number or an interrupt flag. Sub registers are accessed with the functions trx_bit_read and trx_bit_write, which perform 8 bit register accesses and do the multiplexing and masking. The SR_<XYZ> macros contain the offset values, masks and shift values for accessing sub registers in the radio transceiver.

For some of the sub registers, there exist predefined constants which assign symbolic names to numeric values (e.g. TRX_OFF, PLL_ON, RX_ON and SLEEP as state names for the sub register SR_TRX_STATUS).

Example 1 for sub register SR_TRX_STATUS

This example defines the five bit sub register SR_TRX_STATUS, which is located in the register RG_TRX_STATUS.

   #define SR_TRX_STATUS   0x01, 0x1f, 0

       -------------------------------
      | Register 0x01:  RG_TRX_STATUS |
       --- --- --- --- --- --- --- ---
      |   |   |   | v   v   v   v   v |
       --- --- --- --- --- --- --- ---
        7   6   5   4   3   2   1   0
                  [===================]---> SR_TRX_STATUS

                   offset = 0x01
                   mask   = 0x1f
                   shift  =    0
  

Example 2 for sub register SR_TX_AUTO_CRC_ON

This example defines the single bit sub register SR_TX_AUTO_CRC_ON, which is located in the register RG_PHY_TX_PWR.

    #define SR_TX_AUTO_CRC_ON   0x05, 0x80, 7

       -------------------------------
      | Register 0x05:  RG_PHY_TX_PWR |
       --- --- --- --- --- --- --- ---
      | v |   |   |   |   |   |   |   |
       --- --- --- --- --- --- --- ---
        7   6   5   4   3   2   1   0
      [===]-------------------------------> SR_TX_AUTO_CRC_ON

                   offset = 0x05
                   mask   = 0x80
                   shift  =    7
   

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